Experiments with a Program Timing Tool Based on Source-Level Timing Schema
Computer - Special issue on real-time systems
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Performance analysis of embedded software using implicit path enumeration
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Region-based compilation: introduction, motivation, and initial experience
International Journal of Parallel Programming - Special issue on instruction-level parallel processing—part I
Advanced compiler design and implementation
Advanced compiler design and implementation
Guest Editorial: A Review of Worst-Case Execution-TimeAnalysis
Real-Time Systems - Special issue on worst-case execution-time analysis
Conversion of control dependence to data dependence
POPL '83 Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Introducing the IA-64 Architecture
IEEE Micro
Processor Pipelines and Their Properties for Static WCET Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Analysis of the Execution Time Unpredictability caused by Dynamic Branch Prediction
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
Pipeline Timing Analysis Using a Trace-Driven Simulator
RTCSA '99 Proceedings of the Sixth International Conference on Real-Time Computing Systems and Applications
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
A Modular & Retargetable Framework for Tree-Based WCET Analysis
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
Predictable and Efficient Virtual Addressing for Safety-Critical Real-Time Systems
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
Writing Temporally Predictable Code
WORDS '02 Proceedings of the The Seventh IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS 2002)
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Time predictability is an important requirement for real-time embedded application domains such as automotive, air transportation, and multimedia processing. However, the architectural design of modern microprocessors mainly concentrates on improving the average-case performance, which can significantly compromise the time predictability and can make accurate worst-case performance analysis extremely difficult if not impossible.This paper studies the time predictability of VLIW (Very Long Instruction Word) processors and its compiler support. We analyze the impediments to time predictability for VLIW processors and propose compiler-based techniques to address these problems with minimal disturbance on the VLIW hardware design. The VLIW compiler is enhanced to support full if conversion, hyperblock scheduling, and intra-block nop insertion to enable efficient WCET (Worst Case Execution Time) analysis for VLIW processors. Our experiments indicate that the time-predictability of VLIW processor can be improved significantly.