Artificial Intelligence - Special issue on knowledge representation
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Pipeline behavior prediction for superscalar processors by abstract interpretation
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Interval-Based Analysis of Software Processes
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering
Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Pipeline Timing Analysis Using a Trace-Driven Simulator
RTCSA '99 Proceedings of the Sixth International Conference on Real-Time Computing Systems and Applications
Low-level analysis of a portable Java byte code WCET analysis framework
RTCSA '00 Proceedings of the Seventh International Conference on Real-Time Systems and Applications
A Worst Case Timing Analysis Technique for Multiple-Issue Machines
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
A Modular & Retargetable Framework for Tree-Based WCET Analysis
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
Accurate timing analysis by modeling caches, speculation and their interaction
Proceedings of the 40th annual Design Automation Conference
Deadline analysis of interrupt-driven software
Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineering
Deadline Analysis of Interrupt-Driven Software
IEEE Transactions on Software Engineering
A time-predictable VLIW processor and its compiler support
Real-Time Systems
Towards a Statistical Model of a Microprocessor's Throughput by Analyzing Pipeline Stalls
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
Trace acquirement from real-time systems based on WCET analysis
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Analyzing loop paths for execution time estimation
ICDCIT'05 Proceedings of the Second international conference on Distributed Computing and Internet Technology
Sensitivity of cache replacement policies
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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When developing real-time systems, the worst-case execution time (WCET) is a commonly used measure for predicting and analyzing program and system timing behavior. Such estimates should preferrably be provided by static WCET analysis tools. Their analysis is made difficult by features of common processors, such as pipelines and caches.This paper examines the properties of single-issue in-order pipelines, based on a mathematical model of temporal constraints. The key problem addressed is to determine the distance (measured in number of subsequent instructions) over which an instruction can affect the timing behavior of other instructions, and when this effect must be considered in static WCET analysis. We characterize classes of pipelines for which static analysis can safely ignore effects longer than some arbitrary threshold. For other classes of pipelines, pipeline effects can propagate across arbitrary numbers of instructions, making it harder to design safe and precise analysis methods.Based on our results, we discuss how to construct safe WCET analysis methods. We also prove when it is correct to use localworst-case approximations to construct an overall WCET estimate.