Worst Case Execution Time Analysis for a Processor withBranch Prediction
Real-Time Systems - Special issue on worst-case execution-time analysis
Processor Pipelines and Their Properties for Static WCET Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Pipeline Modeling for Timing Analysis
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Modeling Out-of-Order Processors for Software Timing Analysis
RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
Classification of WCET Analysis Techniques
ISORC '05 Proceedings of the Eighth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing
WORDS '05 Proceedings of the 10th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
A Control Theory Approach to Improve the Real-Time Capability of Multi-Threaded Microprocessors
ISORC '08 Proceedings of the 2008 11th IEEE Symposium on Object Oriented Real-Time Distributed Computing
Time-predictable Cache Organization
STFSSD '09 Proceedings of the 2009 Software Technologies for Future Dependable Distributed Systems
Implementing control algorithms within a multithreaded java microcontroller
ARCS'05 Proceedings of the 18th international conference on Architecture of Computing Systems conference on Systems Aspects in Organic and Pervasive Computing
Chip-size evaluation of a multithreaded processor enhanced with a PID controller
SEUS'10 Proceedings of the 8th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
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In this paper we model a thread's throughput, the instruction per cycle rate (IPC rate), running on a general microprocessor as used in common embedded systems. Our model is not limited to a particular microprocessor because our aim is to develop a general model which can be adapted thus fitting to different microprocessor architectures. We include stalls caused by different pipeline obstacles like data dependencies, branch misprediction etc. These stalls involve latency clock cycles blocking the processor. We also describe each kind of stall in detail and develop a statistical model for the throughput including the entire processor pipeline.