Real-time Euclid: a language for reliable real-time systems
IEEE Transactions on Software Engineering - Special issue on reliability and safety in real-time process control
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Experiments with a Program Timing Tool Based on Source-Level Timing Schema
Computer - Special issue on real-time systems
Predicting program execution times by analyzing static and dynamic program paths
Real-Time Systems - Special issue: Real-time languages and language-level timing tools and analysis
Pipelined processors and worst case execution times
Real-Time Systems
Combining static worst-case timing analysis and program proof
Real-Time Systems
Computing Maximum Task Execution Times — A Graph-BasedApproach
Real-Time Systems
Deriving Annotations for Tight Calculation of Execution Time
Euro-Par '97 Proceedings of the Third International Euro-Par Conference on Parallel Processing
Timing Analysis for Data Caches and Set-Associative Caches
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Bounding Loop Iterations for Timing Analysis
RTAS '98 Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium
Tighter Timing Predictions by Automatic Detection and Exploitation of Value-Dependent Constraints
RTAS '99 Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Hades: A Middleware Support for Distributed Safety-Critical Real-Time Applications
ICDCS '98 Proceedings of the The 18th International Conference on Distributed Computing Systems
Retargetable static timing analysis for embedded software
Proceedings of the 14th international symposium on Systems synthesis
Efficient longest executable path search for programs with complex flows and pipeline effects
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Timing analysis of embedded software for speculative processors
Proceedings of the 15th international symposium on System Synthesis
Important Considerations for Execution time Analysis of Dynamic, Periodic Processes
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Are COTS Suitable for Building Distributed Fault-Tolerant Hard Real-Time Systems?
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Pipeline Modeling for Timing Analysis
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Accurate timing analysis by modeling caches, speculation and their interaction
Proceedings of the 40th annual Design Automation Conference
Analysis of the Execution Time Unpredictability caused by Dynamic Branch Prediction
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
Clustered calculation of worst-case execution times
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Experimental Evaluation of Code Properties for WCET Analysis
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Accurate software performance estimation using domain classification and neural networks
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Modeling control speculation for timing analysis
Real-Time Systems
A Contribution to Branch Prediction Modeling in WCET Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A time-predictable execution mode for superscalar pipelines with instruction prescheduling
Proceedings of the 2nd conference on Computing frontiers
Clustered Worst-Case Execution-Time Calculation
IEEE Transactions on Computers
Worst case execution time analysis for synthesized hardware
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Modeling out-of-order processors for WCET analysis
Real-Time Systems
Accounting for cache-related preemption delay in dynamic priority schedulability analysis
Proceedings of the conference on Design, automation and test in Europe
WCET free time analysis of hard real-time systems on multiprocessors: A regular language-based model
Theoretical Computer Science
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Implementing fault-tolerance in real-time programs by automatic program transformations
ACM Transactions on Embedded Computing Systems (TECS)
Challenges in Relational Learning for Real-Time Systems Applications
ILP '08 Proceedings of the 18th international conference on Inductive Logic Programming
Reliability versus performance for critical applications
Journal of Parallel and Distributed Computing
A Context-Parameterized Model for Static Analysis of Execution Times
Transactions on High-Performance Embedded Architectures and Compilers II
Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
Predicated Worst-Case Execution-Time Analysis
Ada-Europe '09 Proceedings of the 14th Ada-Europe International Conference on Reliable Software Technologies
Towards a Statistical Model of a Microprocessor's Throughput by Analyzing Pipeline Stalls
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
Parametric timing analysis and its application to dynamic voltage scaling
ACM Transactions on Embedded Computing Systems (TECS)
Modeling complex flows for worst-case execution time analysis
RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
OTAWA: an open toolbox for adaptive WCET analysis
SEUS'10 Proceedings of the 8th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
Time-triggered buffers for event-based middleware systems
Innovations in Systems and Software Engineering
Branch target buffers: WCET analysis framework and timing predictability
Journal of Systems Architecture: the EUROMICRO Journal
Static WCET analysis based compiler-directed DVS energy optimization in real-time applications
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Tradeoffs between branch mispredictions and comparisons for sorting algorithms
WADS'05 Proceedings of the 9th international conference on Algorithms and Data Structures
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The fundamental requirement forhard real-time systems is that task deadlines be never missed.As a consequence, knowing tasks worst case execution times (WCET)is crucial for such systems. Taking into account modern architecturalfeatures makes it possible to determine tighter WCET bounds thanwith program analysis that ignores such features. While effectsof caches and pipelines on WCET analysis have been extensivelystudied, to our knowledge the effect of the branch predictionon WCET evaluation has not been studied yet. This paper describesa method for statically bounding the number of timing penaltiesdue to erroneous branch predictions. The proposed method is basedon static program analysis and branch target buffer modelling.It consists in collecting information on branch target bufferevolution by considering all possible execution paths of a program.Collected information can then be used to classify control transferinstructions so that their worst case branching cost can be estimatedand incorporated into the program WCET.A method is also given to tightly predict the WCET of loopswhose number of iterations depend on counter variables of outerloops. Experimental results show that the timing penalty dueto wrong branch predictions estimated by the proposed techniqueis close to the real one, which demonstrates the practical applicabilityof our method.