Run-time voltage hopping for low-power real-time systems
Proceedings of the 37th Annual Design Automation Conference
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Worst Case Execution Time Analysis for a Processor withBranch Prediction
Real-Time Systems - Special issue on worst-case execution-time analysis
Hard real-time scheduling for low-energy using stochastic data and DVS processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy-conscious compilation based on voltage scaling
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications
IEEE Design & Test
The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Collaborative Operating System and Compiler Power Management for Real-Time Applications
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
Battery-Driven System Design: A New Frontier in Low Power Design
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints
Proceedings of the conference on Design, automation and test in Europe
Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems
IEEE Transactions on Computers
Power-Aware Scheduling for AND/OR Graphs in Real-Time Systems
IEEE Transactions on Parallel and Distributed Systems
Optimizing the configuration of dynamic voltage scaling points in real-time applications
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Compiler-directed dynamic voltage scaling (DVS) is one of the effective low-power techniques for real-time applications. Using the technique, compiler inserts voltage scaling points into a real-time application, and supply voltage and clock frequency are adjusted to the relationship between the remaining time and the remaining workload at each voltage scaling point. In this paper, based on the WCET (the worst case execution time) analysis tool HEPTANE and the performance/power simulator Sim-Panalyzer, we present a DVS-enabled simulation environment RTLPower (Real-Time Low Power), which integrates static WCET estimation, performance/power simulation, automatically inserting the DVS code into a real-time application, and profile-guided energy optimization. By simulations of some benchmark applications, we prove that the DVS technique and the profile-guided optimization technique significantly reduce energy consumption.