The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Symbolic Cache Analysis for Real-Time Systems
Real-Time Systems - Special issue on worst-case execution-time analysis
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Worst Case Execution Time Analysis for a Processor withBranch Prediction
Real-Time Systems - Special issue on worst-case execution-time analysis
Efficient longest executable path search for programs with complex flows and pipeline effects
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Data flow based cache prediction using local simulation
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Timing Analysis for Data Caches and Set-Associative Caches
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
Analysis of the Impacts of Overestimation Sources on the Accuracy of Worst Case Timing Analysis
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
WCET Analysis of Probabilistic Hard Real-Time Systems
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delivering real-time behaviour
Domain modeling and the duration calculus
A capacity sharing and stealing strategy for open real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
Relative roles of instruction count and cycles per instruction in WCET estimation
Proceedings of the 2nd ACM/SPEC International Conference on Performance engineering
Identifying irreducible loops in the Instrumentation Point Graph
Journal of Systems Architecture: the EUROMICRO Journal
Embedded Systems Design
Estimation of probabilistic bounds on phase CPI and relevance in WCET analysis
Proceedings of the tenth ACM international conference on Embedded software
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This paper presents a quantification of the timing effectsthat advanced processor features like data and instructioncache, pipelines, branch prediction units and out-of-orderexecution units have on the worst-case execution time(WCET) of programs. These features are present in processors(e.g. PowerPC) that are being widely used in embeddedand real-time systems. We present an experimental evaluationof the execution time of a series of synthetic benchmarksand real-life case studies. The execution time is evaluatedusing extensive testing and a simple WCET technique.We show that the most important factor in reduction of executiontime is cache size (both instruction and data cache).Other factors like branch prediction and out-or-order executionhave minimal improvements that is cancelled out bythe pessimism of the analysis. We also argue that some of theperformance gain of advanced processor features also appliesto the worst case and although WCET estimates maybe more pessimistic the overall impact is that they result inlower WCET estimates.