Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Analyzing and visualizing performance of memory hierarchies
Parallel computer systems
The cache performance and optimizations of blocked algorithms
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Performance debugging shared memory multiprocessor programs with MTOOL
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Predicting program execution times by analyzing static and dynamic program paths
Real-Time Systems - Special issue: Real-time languages and language-level timing tools and analysis
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Beyond induction variables: detecting and classifying sequences using a demand-driven SSA form
ACM Transactions on Programming Languages and Systems (TOPLAS)
Worst-case execution time analysis on modern processors
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Performance estimation of embedded software with instruction cache modeling
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Discrete loops and worst case performance
Computer Languages
Symbolic analysis for parallelizing compilers
ACM Transactions on Programming Languages and Systems (TOPLAS)
Worst-case space and time complexity of recursive procedures
Real-Time Systems
Combining static worst-case timing analysis and program proof
Real-Time Systems
Symbolic evaluation for parallelizing compilers
ICS '97 Proceedings of the 11th international conference on Supercomputing
Cache miss equations: an analytical representation of cache misses
ICS '97 Proceedings of the 11th international conference on Supercomputing
Symbolic analysis techniques for program parallelization
Future Generation Computer Systems - Special issue on HPCN '97
Efficient Symbolic Analysis for Parallelizing Compilers and Performance Estimators
The Journal of Supercomputing
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Some Techniques for Solving Recurrences
ACM Computing Surveys (CSUR)
ACM Computing Surveys (CSUR)
Symbolic execution and program testing
Communications of the ACM
Automatic Performance Prediction of Parallel Programs
Automatic Performance Prediction of Parallel Programs
A Discipline of Programming
Data-Flow Frameworks for Worst-Case Execution Time Analysis
Real-Time Systems
Estimating Cache Performance for Sequential and Data Parallel Programs
HPCN Europe '97 Proceedings of the International Conference and Exhibition on High-Performance Computing and Networking
On Estimating and Enhancing Cache Effectiveness
Proceedings of the Fourth International Workshop on Languages and Compilers for Parallel Computing
Symbolic Reaching Definitions Analysis of Ada Programs
Ada-Europe '98 Proceedings of the 1998 Ada-Europe International Conference on Reliable Software Technologies
Cache Behavior Prediction by Abstract Interpretation
SAS '96 Proceedings of the Third International Symposium on Static Analysis
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
A Worst Case Timing Analysis Technique for Multiple-Issue Machines
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Symbolic pointer analysis for detecting memory leaks
PEPM '00 Proceedings of the 2000 ACM SIGPLAN workshop on Partial evaluation and semantics-based program manipulation
A Unified Symbolic Evaluation Framework for Parallelizing Compilers
IEEE Transactions on Parallel and Distributed Systems
Data-Flow Frameworks for Worst-Case Execution Time Analysis
Real-Time Systems
Experimental Evaluation of Code Properties for WCET Analysis
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
A compiler tool to predict memory hierarchy performance of scientific codes
Parallel Computing
Eliminating redundant range checks in GNAT using symbolic evaluation
Ada-Europe'03 Proceedings of the 8th Ada-Europe international conference on Reliable software technologies
Advanced symbolic analysis for compilers: new techniques and algorithms for symbolic program analysis and optimization
Symbolic analysis of imperative programming languages
JMLC'06 Proceedings of the 7th joint conference on Modular Programming Languages
A symbolic analysis framework for static analysis of imperative programming languages
Journal of Systems and Software
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Cachesimpose a major problem for predicting execution times of real-timesystems since the cache behavior depends on the history of previousmemory references. Too pessimistic assumptions on cache hitscan obtain worst-case execution time estimates that are prohibitivefor real-time systems. This paper presents a novel approach forderiving a highly accurate analytical cache hit function forC-programs at compile-time based on the assumption that no externalcache interference (e.g. process dispatching or DMA activity)occurs. First, a symbolic tracefile of an instrumented C-programis generated based on symbolic evaluation, which is a statictechnique to determine the dynamic behavior of programs. Allmemory references of a program are described by symbolic expressionsand recurrences and stored in chronological order in the symbolictracefile. Second, a cache hit function for several cache architecturesis computed based on a cache evaluation technique. Our approachgoes beyond previous work by precisely modelling program controlflow and program unknowns, modelling large classes of cache architectures,and providing very accurate cache hit predictions. Examples forthe SPARC architecture are used to illustrate the accuracy andeffectiveness of our symbolic cache prediction.