A compiler tool to predict memory hierarchy performance of scientific codes

  • Authors:

  • B. B. Fraguela;R. Doallo;J. Touriño;E. L. Zapata

  • Affiliations:

  • Depto. de Electrónica e Sistemas, Facultade de Informática, Universidade da Coruña, Campus de Elviña s/n, 15071 A Coruña, Spain;Depto. de Electrónica e Sistemas, Facultade de Informática, Universidade da Coruña, Campus de Elviña s/n, 15071 A Coruña, Spain;Depto. de Electrónica e Sistemas, Facultade de Informática, Universidade da Coruña, Campus de Elviña s/n, 15071 A Coruña, Spain;Depto. de Arquitectura de Computadores, Complejo Tecnológico Campus de Teatinos, Universidad de Málaga, 29080 Málaga, Spain

  • Venue:
  • Parallel Computing
  • Year:
  • 2004

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Abstract

The study and understanding of memory hierarchy behavior is essential, as it is critical to current systems performance. The design of optimising environments and compilers, which allow the guidance of program transformation applications in order to improve cache performance with as little user intervention as possible, is particularly interesting. In this paper we introduce a fast analytical modelling technique that is suitable for arbitrary set-associative caches with LRU replacement policy, which overcomes weak points of other approaches found in the literature. The model was integrated in the Polaris parallelizing compiler, to allow automated analysis of loop-oriented scientific codes and to drive code optimizations. Results from detailed validations using well-known benchmarks show that the model predictions are usually very accurate and that the code optimizations proposed by the model are always, or nearly always, optimal.