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Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
The Spring System: Integrated Support for Complex Real-TimeSystems
Real-Time Systems
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Timing Analysis for Data and Wrap-Around Fill Caches
Real-Time Systems
Supporting Timing Analysis by Automatic Bounding of LoopIterations
Real-Time Systems - Special issue on worst-case execution-time analysis
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Worst Case Execution Time Analysis for a Processor withBranch Prediction
Real-Time Systems - Special issue on worst-case execution-time analysis
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Retargetable static timing analysis for embedded software
Proceedings of the 14th international symposium on Systems synthesis
Efficient longest executable path search for programs with complex flows and pipeline effects
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Data cache locking for higher program predictability
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
Ensuring integrity and service availability in a web-based control laboratory
Real-time system security
Clustered calculation of worst-case execution times
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Experimental Evaluation of Code Properties for WCET Analysis
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Data Caches in Multitasking Hard Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior
IEEE Transactions on Computers
Automatic generation of peephole optimizations
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Compositional static instruction cache simulation
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Clustered Worst-Case Execution-Time Calculation
IEEE Transactions on Computers
Improving WCET by applying a WC code-positioning optimization
ACM Transactions on Architecture and Code Optimization (TACO)
Improving WCET by applying worst-case path optimizations
Real-Time Systems
WCET estimation for executables in the presence of data caches
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Data cache locking for tight timing calculations
ACM Transactions on Embedded Computing Systems (TECS)
Relative competitive analysis of cache replacement policies
Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
Exploiting stack distance to estimate worst-case data cache performance
Proceedings of the 2009 ACM symposium on Applied Computing
Abstract Interpretation of FIFO Replacement
SAS '09 Proceedings of the 16th International Symposium on Static Analysis
Probabilistic modeling of data cache behavior
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Multicore-aware hybrid code positioning to reduce worst-case execution time
Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture
Experimentation of WCET computation on both ends of automotive processor range
Proceedings of the 1st Workshop on Critical Automotive applications: Robustness & Safety
Parametric timing analysis and its application to dynamic voltage scaling
ACM Transactions on Embedded Computing Systems (TECS)
Modeling complex flows for worst-case execution time analysis
RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
Branch target buffers: WCET analysis framework and timing predictability
Journal of Systems Architecture: the EUROMICRO Journal
Cache-related preemption delay via useful cache blocks: Survey and redefinition
Journal of Systems Architecture: the EUROMICRO Journal
Static timing analysis for hard real-time systems
VMCAI'10 Proceedings of the 11th international conference on Verification, Model Checking, and Abstract Interpretation
Static analysis of the worst-case memory performance for irregular codes with indirections
ACM Transactions on Architecture and Code Optimization (TACO)
Static analysis of worst-case stack cache behavior
Proceedings of the 21st International conference on Real-Time Networks and Systems
Address independent estimation of the boundaries of cache performance
Microprocessors & Microsystems
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The contributions of this paper are twofold. First, an automatic tool-based approach is described to bound worst-case data cache performance. The given approach works on fully optimized code, performs the analysis over the entire control flow of a program, detects and exploits both spatial and temporal locality within data references, produces results typically within a few seconds, and estimates, on average, 30% tighter WCET bounds than can be predicted without analyzing data cache behavior. Results obtained by running the system on representative programs are presented and indicate that timing analysis of data cache behavior can result in significantly tighter worst-case performance predictions. Second, a framework to bound worst-case instruction cache performance for set-associative caches is formally introduced and operationally described. Results of incorporating instruction cache predictions within pipeline simulation show that timing predictions for set-associative caches remain just as Tight as predictions for direct-mapped caches. The cache simulation overhead scales linearly with increasingassociativity.