Reasoning About Time in Higher-Level Language Software
IEEE Transactions on Software Engineering
Calculating the maximum, execution time of real-time programs
Real-Time Systems
A partial evaluator for the Maruti hard real-time system
Real-Time Systems - Special issue: Real-time languages and language-level timing tools and analysis
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering
Deriving Annotations for Tight Calculation of Execution Time
Euro-Par '97 Proceedings of the Third International Euro-Par Conference on Parallel Processing
On Predicting Data Cache Behavior for Real-Time Systems
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Cache Behavior Prediction by Abstract Interpretation
SAS '96 Proceedings of the Third International Symposium on Static Analysis
Efficient worst case timing analysis of data caching
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Timing Analysis for Data Caches and Set-Associative Caches
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Bounding Loop Iterations for Timing Analysis
RTAS '98 Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium
Efficient microarchitecture modeling and path analysis for real-time software
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
A Worst Case Timing Analysis Technique for Multiple-Issue Machines
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Fast instruction cache analysis via static cache simulation
SS '95 Proceedings of the 28th Annual Simulation Symposium
SimICS/sun4m: a virtual workstation
ATEC '98 Proceedings of the annual conference on USENIX Annual Technical Conference
Retargetable static timing analysis for embedded software
Proceedings of the 14th international symposium on Systems synthesis
Automatic Accurate Cost-Bound Analysis for High-Level Languages
IEEE Transactions on Computers
Pipeline Modeling for Timing Analysis
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Timing Analysis of Assembler Code Control-Flow Paths
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
Clustered calculation of worst-case execution times
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Compositional static instruction cache simulation
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Measuring the cache interference cost in preemptive real-time systems
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Adaptive code unloading for resource-constrained JVMs
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
HOIST: a system for automatically deriving static analyzers for embedded systems
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Modeling control speculation for timing analysis
Real-Time Systems
A time-predictable execution mode for superscalar pipelines with instruction prescheduling
Proceedings of the 2nd conference on Computing frontiers
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Clustered Worst-Case Execution-Time Calculation
IEEE Transactions on Computers
Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Deriving abstract transfer functions for analyzing embedded software
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Modeling out-of-order processors for WCET analysis
Real-Time Systems
Timing analysis for preemptive multitasking real-time systems with caches
ACM Transactions on Embedded Computing Systems (TECS)
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
Proceedings of the conference on Design, automation and test in Europe
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Exploring locking & partitioning for predictable shared caches on multi-cores
Proceedings of the 45th annual Design Automation Conference
A Context-Parameterized Model for Static Analysis of Execution Times
Transactions on High-Performance Embedded Architectures and Compilers II
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Semi-automatic derivation of timing models for WCET analysis
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Symbolic simulation on complicated loops for WCET path analysis
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
Path-sensitive resource analysis compliant with assertions
Proceedings of the Eleventh ACM International Conference on Embedded Software
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Previouslypublished methods for estimation of the worst-case executiontime on high-performance processors with complex pipelines andmulti-level memory hierarchies result in overestimations owingto insufficient path and/or timing analysis. This does not onlygive rise to poor utilization of processing resources but alsoreduces the schedulability in real-time systems. This paper presentsa method that integrates path and timing analysis to accuratelypredict the worst-case execution time for real-time programson high-performance processors. The unique feature of the methodis that it extends cycle-level architectural simulation techniquesto enable symbolic execution with unknown input data values;it uses alternative instruction semantics to handle unknown operands.We show that the method can exclude many infeasible (or non-executable)program paths and can calculate path information, such as boundson number of loop iterations, without the need for manual annotationsof programs. Moreover, the method is shown to accurately analyzetiming properties of complex features in high-performance processorsusing multiple-issue pipelines and instruction and data caches.The combined path and timing analysis capability is shown toderive exact estimates of the worst-case execution time forsix out of seven programs in our benchmark suite.