An extendible approach for analyzing fixed priority hard real-time tasks
Real-Time Systems
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OSDI '96 Proceedings of the second USENIX symposium on Operating systems design and implementation
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Journal of the ACM (JACM)
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RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
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Performance guarantees can be given to tasks in an embedded system by ensuring that access to each shared resource is mediated by an appropriate scheduler. However, almost all previous work on CPU scheduling has focused on thread-level scheduling, resulting in systems that are vulnerable to a lower-level form of overload that occurs when too many interrupts arrive. This paper describes three new techniques, two software-based and one hardware-based, for creating systems that delay or drop excessive interrupt requests before they can overload a processor. Our interrupt schedulers bound both the amount of work performed in interrupt context and its granularity, making it possible to provide strong progress guarantees to thread-level processing. We show that our solutions work and are efficient when implemented on embedded processors. We have also taken a description for a microprocessor in VHDL, modified it to include logic that prevents interrupt overload, synthesized the processor, and verified that it works using simulation. By allowing developers to avoid making assumptions about the worst-case interrupt rates of peripherals, our work fills an important gap in the chain of reasoning leading to a validated system. These techniques cannot replace careful system design, but they do provide a last-ditch safety guarantee in the presence of a serious malfunction.