ACM Transactions on Computer Systems (TOCS)
The effect of context switches on cache performance
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The interaction of architecture and operating system design
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Performance analysis of embedded software using implicit path enumeration
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling
IEEE Transactions on Computers
Power analysis of embedded operating systems
Proceedings of the 37th Annual Design Automation Conference
Cache Aware Pre-Runtime Scheduling
Real-Time Systems
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
An optimal memory allocation scheme for scratch-pad-based embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Cache Behavior Prediction by Abstract Interpretation
SAS '96 Proceedings of the Third International Symposium on Static Analysis
Run-time modeling and estimation of operating system power consumption
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Data cache locking for higher program predictability
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Performance Analysis of a RTOS by Emulation of an Embedded System
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Low-Complexity Algorithms for Static Cache Locking in Multitasking Hard Real-Time Systems
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
Energy characterization of embedded real-time operating systems
Compilers and operating systems for low power
Context switch overheads for Linux on ARM platforms
Proceedings of the 2007 workshop on Experimental computer science
Context switch overheads on mobile device platforms
ecs'07 Experimental computer science on Experimental computer science
Observations on power-efficiency trends in mobile communication devices
EURASIP Journal on Embedded Systems
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Increasing the determinism in real-time operating systems for ERC32 architecture
SEPADS'06 Proceedings of the 5th WSEAS International Conference on Software Engineering, Parallel and Distributed Systems
Cache partitioning for energy-efficient and interference-free embedded multitasking
ACM Transactions on Embedded Computing Systems (TECS)
An experimental comparison of different real-time schedulers on multicore systems
Journal of Systems and Software
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Caches exploits locality of references to reduce memory access latencies and thereby improve processor performance. When an operating system switches application task or performs other kernel services, the assumption of locality may be violated because the instructions and data may no longer be in the cache when the preempted operation is resumed. Thus, these operations have an additional cache interference cost that must be taken into account when calculating or estimating the performance and responsiveness of the system.In this paper we present a simulation framework suitable for examining the cache interference cost in preemptive real-time systems. Using this framework we measure the interference cost for operating system services and a set of embedded benchmarks.The simulations show that there are a significant performance gap between the best- and worst case execution times even for simple hardware architectures. Also, the worst-case performance of some software modules was found to be more or less independent of the cache configuration. These results can be used to get a better understanding of the execution behavior of preemptive real-time systems and can serve as guidelines for choosing suitable cache configurations.