Scheduling Processes with Release Times, Deadlines, Precedence and Exclusion Relations
IEEE Transactions on Software Engineering
Calculating the maximum, execution time of real-time programs
Real-Time Systems
An extendible approach for analyzing fixed priority hard real-time tasks
Real-Time Systems
Static cache simulation and its applications
Static cache simulation and its applications
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Compiler Design
Priority Inheritance Protocols: An Approach to Real-Time Synchronization
IEEE Transactions on Computers
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering
Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Cache Behavior Prediction by Abstract Interpretation
SAS '96 Proceedings of the Third International Symposium on Static Analysis
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Efficient microarchitecture modeling and path analysis for real-time software
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Measuring the cache interference cost in preemptive real-time systems
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Adaptive code unloading for resource-constrained JVMs
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
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Wepresent a novel pre-runtime scheduling method for uniprocessorswhich precisely takes the effects of task switching on the processorcache into consideration. Tasks are modelled as a sequence ofnon preemptable segments with precedence constraints. The cachebehavior of each task segment is statically determined by abstractinterpretation. For the sake of efficiency, the scheduling algorithmuses a heuristically guided search strategy. Each time a newtask segment is added to a partial schedule, its worst case executiontime is calculated based on the cache state at the end of thepreceding partial schedule.