Data Caches in Multitasking Hard Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Measuring the cache interference cost in preemptive real-time systems
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Adaptive code unloading for resource-constrained JVMs
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Multiple process execution in cache related preemption delay analysis
Proceedings of the 4th ACM international conference on Embedded software
Scalable precision cache analysis for preemptive scheduling
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Polychronous design of embedded real-time applications
ACM Transactions on Software Engineering and Methodology (TOSEM)
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
Proceedings of the conference on Design, automation and test in Europe
Scalable precision cache analysis for real-time software
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Compile-time decided instruction cache locking using worst-case execution paths
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Cache leakage control mechanism for hard real-time systems
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Data cache locking for tight timing calculations
ACM Transactions on Embedded Computing Systems (TECS)
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Exploring locking & partitioning for predictable shared caches on multi-cores
Proceedings of the 45th annual Design Automation Conference
A data centered approach for cache partitioning in embedded real-time database system
WSEAS Transactions on Computers
Cache-aware timing analysis of streaming applications
Real-Time Systems
Instruction cache locking inside a binary rewriter
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Embedded Computing Systems (TECS)
Instruction cache locking using temporal reuse profile
Proceedings of the 47th Design Automation Conference
Tightening the bounds on feasible preemptions
ACM Transactions on Embedded Computing Systems (TECS)
Predictable task migration for locked caches in multi-core systems
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
An algorithm for deciding minimal cache sizes in real-time systems
Proceedings of the 13th annual conference on Genetic and evolutionary computation
Journal of Systems Architecture: the EUROMICRO Journal
Joint task assignment and cache partitioning with cache locking for WCET minimization on MPSoC
Journal of Parallel and Distributed Computing
Instruction cache locking for multi-task real-time embedded systems
Real-Time Systems
Improving interrupt response time in a verifiable protected microkernel
Proceedings of the 7th ACM european conference on Computer Systems
Dynamic Cache Reconfiguration for Soft Real-Time Systems
ACM Transactions on Embedded Computing Systems (TECS)
WCET-centric partial instruction cache locking
Proceedings of the 49th Annual Design Automation Conference
WCET-aware static locking of instruction caches
Proceedings of the Tenth International Symposium on Code Generation and Optimization
Instruction Cache Locking for Embedded Systems using Probability Profile
Journal of Signal Processing Systems
Static task partitioning for locked caches in multi-core real-time systems
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Optimising task layout to increase schedulability via reduced cache related pre-emption delays
Proceedings of the 20th International Conference on Real-Time and Network Systems
Sensitivity of cache replacement policies
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
A cache design for probabilistically analysable real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
Integrated instruction cache analysis and locking in multitasking real-time systems
Proceedings of the 50th Annual Design Automation Conference
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
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Cache memories have been extensively used to bridge the gap between high speed processors and relatively slow main memories. However, they are a source of predictability problems because of their dynamic and adaptive behavior, and thus need special attention to be used in hard-real time systems. A lot of progress has been achieved in the last ten years to statically predict the worst-case behavior of applications with respect to caches in order to determine safe and precise bounds on tasks worst-case execution times (WCETs) and cache-related preemption delays. An alternative approach to cope with caches in real-time systems is to statically lock their contents such that memory access times and cache-related preemption times are predictable. In this paper, we propose two low-complexity algorithms for selecting the contents of statically-locked caches. We evaluate their performances and compare them with those of a state of the art static cache analysis method.