Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Bounding Cache-Related Preemption Delay for Real-Time Systems
IEEE Transactions on Software Engineering
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Low-Complexity Algorithms for Static Cache Locking in Multitasking Hard Real-Time Systems
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
Real Time Scheduling Theory: A Historical Perspective
Real-Time Systems
Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
Estimating the Worst-Case Energy Consumption of Embedded Software
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
Handbook of Constraint Programming (Foundations of Artificial Intelligence)
Handbook of Constraint Programming (Foundations of Artificial Intelligence)
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
Proceedings of the conference on Design, automation and test in Europe
Compile-time decided instruction cache locking using worst-case execution paths
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Energy-Efficient Scheduling for Real-Time Systems on Dynamic Voltage Scaling (DVS) Platforms
RTCSA '07 Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Data cache locking for tight timing calculations
ACM Transactions on Embedded Computing Systems (TECS)
Studying the Applicability of the Scratchpad Memory Management Unit
RTAS '10 Proceedings of the 2010 16th IEEE Real-Time and Embedded Technology and Applications Symposium
Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems
RTCSA '10 Proceedings of the 2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications
Journal of Systems Architecture: the EUROMICRO Journal
Cache Related Pre-emption Delay Aware Response Time Analysis for Fixed Priority Pre-emptive Systems
RTSS '11 Proceedings of the 2011 IEEE 32nd Real-Time Systems Symposium
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In real-time systems, time is usually so critical that other parameters such as energy consumption are often not even considered. However, optimizing the worst energy consumption case can be a key factor in systems with severe power-supply limitations. In this paper we study several memory architectures using combined time and energy optimization models for real-time multitasking systems. Each task is modeled using Lock-MS, a method to optimize the WCET of a task, with an added set of constraints to model in the same way the WCEC (worst case energy consumption). Our tested hardware components focus on instruction fetching, including a lockable cache, a line buffer and a sequential prefetch buffer. We test a variety of instruction fetch alternatives optimizing time and energy consumption. Our results show that the accuracy of the estimation of the number of context switches in the worst case may affect very much the resulting WCEC (up to 8 times in our experiments) and that optimizing the WCEC may provide similar execution times than optimizing the WCET, with up to 5 times less energy consumption Additionally optimization functions combining WCET and WCEC with different weights show very interesting WCET-WCEC trade-offs. This confirms that methodologies testing such optimizations at design time could be very helpful to provide a precise system set-up.