Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Reconfigurable caches and their application to media processing
Proceedings of the 27th annual international symposium on Computer architecture
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Bounding Cache-Related Preemption Delay for Real-Time Systems
IEEE Transactions on Software Engineering
Software-assisted cache replacement mechanisms for embedded systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A Dynamic Programming Algorithm for Cache Memory Partitioning for Real-Time Systems
IEEE Transactions on Computers
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Low-Complexity Algorithms for Static Cache Locking in Multitasking Hard Real-Time Systems
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
Real Time Scheduling Theory: A Historical Perspective
Real-Time Systems
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
Handbook of Constraint Programming (Foundations of Artificial Intelligence)
Handbook of Constraint Programming (Foundations of Artificial Intelligence)
Compile-time decided instruction cache locking using worst-case execution paths
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Exploring locking & partitioning for predictable shared caches on multi-cores
Proceedings of the 45th annual Design Automation Conference
Avoiding the WCET Overestimation on LRU Instruction Cache
RTCSA '08 Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
On using locking caches in embedded real-time systems
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Integrated instruction cache analysis and locking in multitasking real-time systems
Proceedings of the 50th Annual Design Automation Conference
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
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In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is very complex with variable latency hardware, such as instruction cache memories, or, to a lesser extent, the line buffers usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. The difficulty in these cache-locking methods lies in obtaining a good selection of the memory lines to be locked into cache. In this paper, we propose an ILP-based method to select the best lines to be loaded and locked into the instruction cache at each context switch (dynamic locking), taking into account both intra-task and inter-task interferences, and we compare it with static locking. Our results show that, without cache, the spatial locality captured by a line buffer doubles the performance of the processor. When adding a lockable instruction cache, dynamic locking systems are schedulable with a cache size between 12.5% and 50% of the cache size required by static locking. Additionally, the computation time of our analysis method is not dependent on the number of possible paths in the task. This allows us to analyze large codes in a relatively short time (100KB with 10^6^5 paths in less than 3min).