Program optimization for instruction caches
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Profile guided code positioning
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
Abstract execution: a technique for efficiently tracing programs
Software—Practice & Experience
Experiments with a Program Timing Tool Based on Source-Level Timing Schema
Computer - Special issue on real-time systems
Optimally profiling and tracing programs
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Pipelined processors and worst case execution times
Real-Time Systems
Compile time instruction cache optimizations
ACM SIGARCH Computer Architecture News - Special issue: panel sessions of the 1991 workshop on multithreaded computers
A retargetable technique for predicting execution time of code segments
Real-Time Systems - Special issue: dependability of real-time software
EEL: machine-independent executable editing
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Worst-case execution time analysis on modern processors
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Abstract interpretation: a semantics-based tool for program analysis
Handbook of logic in computer science (vol. 4)
Static cache simulation and its applications
Static cache simulation and its applications
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Cache behavior prediction by abstract interpretation
Science of Computer Programming
ACM Computing Surveys (CSUR)
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Computer Architecture: Pipelined and Parallel Processor Design
Computer Architecture: Pipelined and Parallel Processor Design
Compiler Design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering
On Predicting Data Cache Behavior for Real-Time Systems
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Generation of Efficient Interprocedural Analyzers with PAG
SAS '95 Proceedings of the Second International Symposium on Static Analysis
Cache Behavior Prediction by Abstract Interpretation
SAS '96 Proceedings of the Third International Symposium on Static Analysis
Efficient worst case timing analysis of data caching
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Timing Analysis for Data Caches and Set-Associative Caches
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Worst case timing analysis of RISC processors: R3000/R3010 case study
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Efficient microarchitecture modeling and path analysis for real-time software
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Program path analysis to bound cache-related preemption delay in preemptive real-time systems
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
New directions in compiler technology for embedded systems (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Associative caches in formal software timing analysis
Proceedings of the 39th annual Design Automation Conference
Automatic Accurate Cost-Bound Analysis for High-Level Languages
IEEE Transactions on Computers
PROPAN: A Retargetable System for Postpass Optimisations and Analyses
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Data cache locking for higher program predictability
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Data Caches in Multitasking Hard Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Abstraction of assembler programs for symbolic worst case execution time analysis
Proceedings of the 41st annual Design Automation Conference
Compositional static instruction cache simulation
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Multiple process execution in cache related preemption delay analysis
Proceedings of the 4th ACM international conference on Embedded software
Formal Methods for Integration of Automotive Software
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Context Sensitive Performance Analysis of Automotive Applications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Modeling a system controller for timing analysis
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
WCET estimation for executables in the presence of data caches
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Timing predictability of cache replacement policies
Real-Time Systems
Data cache locking for tight timing calculations
ACM Transactions on Embedded Computing Systems (TECS)
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Relative competitiveness of cache replacement policies
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Relative competitive analysis of cache replacement policies
Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
Abstract Interpretation with Applications to Timing Validation
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Abstract Interpretation of FIFO Replacement
SAS '09 Proceedings of the 16th International Symposium on Static Analysis
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multicore-aware hybrid code positioning to reduce worst-case execution time
Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture
Resilience analysis: tightening the CRPD bound for set-associative caches
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Worst-case execution time analysis for a Java processor
Software—Practice & Experience
An appreciation of the work of Reinhard Wilhelm
Program analysis and compilation, theory and practice
Parametric timing analysis and its application to dynamic voltage scaling
ACM Transactions on Embedded Computing Systems (TECS)
Cache and pipeline sensitive fixed priority scheduling for preemptive real-time systems
RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
Cache persistence analysis: a novel approachtheory and practice
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Branch target buffers: WCET analysis framework and timing predictability
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
Joint task assignment and cache partitioning with cache locking for WCET minimization on MPSoC
Journal of Parallel and Distributed Computing
Making DRAM refresh predictable
Real-Time Systems
Cache analysis in presence of pointer-based data structures
ACM SIGBED Review - Work-in-Progress (WiP) Session of the 23rd Euromicro Conference on Real-Time Systems (ECRTS 2011)
A synergetic approach to accurate analysis of cache-related preemption delay
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
WCET-driven cache-aware code positioning
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Combining measures for temporal and spatial locality
ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
Static timing analysis for hard real-time systems
VMCAI'10 Proceedings of the 11th international conference on Verification, Model Checking, and Abstract Interpretation
Worst-case execution time analysis-driven object cache design
Concurrency and Computation: Practice & Experience
On abstractions for timing analysis in the K framework
FOPARA'11 Proceedings of the Second international conference on Foundational and Practical Aspects of Resource Analysis
PRETI: partitioned real-time shared cache for mixed-criticality real-time systems
Proceedings of the 20th International Conference on Real-Time and Network Systems
Meeting real-time requirements with multi-core processors
SAFECOMP'12 Proceedings of the 2012 international conference on Computer Safety, Reliability, and Security
Data cache organization for accurate timing analysis
Real-Time Systems
Cache persistence analysis: Theory and practice
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Hybrid source-level simulation of data caches using abstract cache models
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Computation takes time, but how much?
Communications of the ACM
Static analysis of worst-case stack cache behavior
Proceedings of the 21st International conference on Real-Time Networks and Systems
| Hi-index | 0.02 |
Abstractinterpretation is a technique for the static detection of dynamicproperties of programs. It is semantics based, that is, it computesapproximative properties of the semantics of programs. On thisbasis, it supports correctness proofs of analyses. It replacescommonly used ad hoc techniques by systematic, provable ones,and it allows for the automatic generation of analyzers fromspecifications by existing tools. In this work, abstract interpretationis applied to the problem of predicting the cache behavior ofprograms. Abstract semantics of machine programs are definedwhich determine the contents of caches. For interprocedural analysis,existing methods are examined and a new approach that is especiallytailored for the cache analysis is presented. This allows fora static classification of the cache behavior of memory referencesof programs. The calculated information can be used to improveworst case execution time estimations. It is possible to analyzeinstruction, data, and combined instruction/data caches for common(re)placement and write strategies. Experimental results arepresented that demonstrate the applicability of the analyses.