Abstract execution: a technique for efficiently tracing programs
Software—Practice & Experience
Pipeline behavior prediction for superscalar processors by abstract interpretation
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Cache behavior prediction by abstract interpretation
Science of Computer Programming
Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Cache-Sensitive Pre-runtime Scheduling
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
A cache-aware scheduling algorithm for embedded systems
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
Multiple process execution in cache related preemption delay analysis
Proceedings of the 4th ACM international conference on Embedded software
Scalable precision cache analysis for real-time software
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Optimal task placement to improve cache performance
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Delay composition in preemptive and non-preemptive real-time pipelines
Real-Time Systems
Parametric timing analysis and its application to dynamic voltage scaling
ACM Transactions on Embedded Computing Systems (TECS)
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Current schedulability analyses for preemptive systems consider cache behaviour by adding preemption caused cache reload costs. Thereby, they ignore the fact that delays due to cache misses often have a reduced impact because of pipeline effects. In this paper, these methods are called isolated. Pipeline-related preemption costs are not considered at all in current schedulability analyses. This paper presents two cache and pipeline sensitive response time analysis methods for fixed priority preemptive scheduling. The first is an isolated method. The second method incorporates the preemption caused cache costs into the Worst-Case Execution Time (WCET) of the preempted task. This allows for the compensation of delays due to cache misses by pipeline effects. It is shown that the applicability of isolated approaches is limited to a certain class of CPUs. Practical experiments are used to compare both methods.