Parametric timing analysis and its application to dynamic voltage scaling

Authors:
Sibin Mohan;Frank Mueller;Michael Root;William Hawkins;Christopher Healy;David Whalley;Emilio Vivancos
Affiliations:
North Carolina State University, Raleigh, NC;North Carolina State University, Raleigh, NC;Furman University, Greenville, SC;Furman University, Greenville, SC;Furman University, Greenville, SC;Florida State University, Tallahassee, FL;Universidad Politecnica de Valencia, Valencia, Spain
Venue:
ACM Transactions on Embedded Computing Systems (TECS)
Year:
2011

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Cited 1

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Abstract

Embedded systems with real-time constraints depend on a priori knowledge of worst-case execution times (WCETs) to determine if tasks meet deadlines. Static timing analysis derives bounds on WCETs but requires statically known loop bounds. This work removes the constraint on known loop bounds through parametric analysis expressing WCETs as functions. Tighter WCETs are dynamically discovered to exploit slack by dynamic voltage scaling (DVS) saving 60% to 82% energy over DVS-oblivious techniques and showing savings close to more costly dynamic-priority DVS algorithms. Overall, parametric analysis expands the class of real-time applications to programs with loop-invariant dynamic loop bounds while retaining tight WCET bounds.