Practical Voltage-Scaling for Fixed-Priority RT-Systems

  • Authors:
  • Saowanee Saewong;Ragunathan (Raj) Rajkumar

  • Affiliations:
  • -;-

  • Venue:
  • RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
  • Year:
  • 2003

Quantified Score

Hi-index 0.01

Visualization

Abstract

In CMOS circuits, power consumption is proportional tothe product of the frequency and the square of the supplyvoltage. Hence, any reductions in the operating frequencyof the processor and its supply voltage can lead to significantsavings in energy consumption (and heat dissipation)but cause longer execution times. The application of dynamicvoltage scaling (DVS) techniques to real-time systemsmust therefore attempt to minimize energy while guaranteeingthe schedulability of the real-time tasks. In thispaper, we study the effect of limited number of operating frequencieson the performance of voltage-scaling algorithms.The optimal frequency grid which minimizes the effect ofdiscrete operating frequencies is also derived. We then proposefour alternative voltage-scaling schemes, Sys-Clock,PM-Clock, Opt-Clock and DPM-Clock. Each scheme issuitable for different hardware configuration which mayhave high or low voltage-scaling overhead and differenttaskset characteristics. We have implemented our voltage-scalingschemes on CMU's real-time OS, Linux/RK, on the3700 series Compaq iPAQ and a 733MHz XScale BRHboard modified to support voltage-scaling.