Comparing algorithm for dynamic speed-setting of a low-power CPU
MobiCom '95 Proceedings of the 1st annual international conference on Mobile computing and networking
The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Hard real-time scheduling for low-energy using stochastic data and DVS processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Real-time dynamic voltage scaling for low-power embedded operating systems
SOSP '01 Proceedings of the eighteenth ACM symposium on Operating systems principles
Energy-conserving feedback EDF scheduling for embedded systems with real-time constraints
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Control-theoretic dynamic frequency and voltage scaling for multimedia workloads
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
A Fast Resource Synthesis Technique for Energy-Efficient Real-Time Systems
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
A control-theoretic approach to dynamic voltage scheduling
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Power-Aware Scheduling for Periodic Real-Time Tasks
IEEE Transactions on Computers
Procrastination scheduling in fixed priority real-time systems
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Feedback EDF Scheduling Exploiting Dynamic Voltage Scaling
RTAS '04 Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium
Energy - Responsiveness Tradeoffs for Real-Time Systems with Mixed Workload
RTAS '04 Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium
Optimized Slowdown in Real-Time Task Systems
ECRTS '04 Proceedings of the 16th Euromicro Conference on Real-Time Systems
The design and application of the PowerPC 405LP energy-efficient system-on-a-chip
IBM Journal of Research and Development
Policies for dynamic clock scheduling
OSDI'00 Proceedings of the 4th conference on Symposium on Operating System Design & Implementation - Volume 4
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Performance specifications and metrics for adaptive real-time systems
RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
Energy aware kernel for hard real-time systems
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Frequency-aware energy optimization for real-time periodic and aperiodic tasks
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Exploiting synchronous and asynchronous DVS for feedback EDF scheduling on an embedded platform
ACM Transactions on Embedded Computing Systems (TECS)
Multiprocessor frequency locking for real-time task synchronization
Proceedings of the 2008 ACM symposium on Applied computing
Parametric timing analysis and its application to dynamic voltage scaling
ACM Transactions on Embedded Computing Systems (TECS)
xTune: A formal methodology for cross-layer tuning of mobile embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Hi-index | 0.00 |
Recent processor support for dynamic frequency and voltage scaling (DVS) allows software to affect power consumption by varying execution frequency and supply voltage on the fly. However, processors generally enter a sleep state while transitioning between frequencies/voltages. In this paper, we examine the merits of hardware/software co-design for a feedback DVS algorithm and a novel processor capable of executing instructions during frequency/voltage transitions. We study several power-aware feedback schemes based on earliest-deadline-first (EDF) scheduling that adjust the system behavior dynamically for different workload characteristics. An infrastructure for investigating several hard real-time DVS schemes, including our feedback DVS algorithm, is implemented on an IBM PowerPC 405LP embedded board. Architecture and algorithm overhead is assessed for different DVS schemes. Measurements on the experimentation board provide a quantitative assessment of the potential of energy savings for DVS algorithms as opposed to prior simulation work that could only provide trends. Energy consumption, measured through a data acquisition board, indicates a considerable potential for real-time DVS scheduling algorithms to lower energy up to 64% over the naïve DVS scheme. Our feedback DVS algorithm saves at least as much and often considerably more energy than previous DVS algorithms with peak savings of an additional 24% energy reduction. To the best of our knowledge, this is the first comparative study of real-time DVS algorithms on a concrete micro-architecture and the first evaluation of asynchronous DVS switching.