Reasoning About Time in Higher-Level Language Software
IEEE Transactions on Software Engineering
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Predicting deterministic execution times of real-time programs
Predicting deterministic execution times of real-time programs
Discrete loops and worst case performance
Computer Languages
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Performance Analysis of Real-Time Embeded Software
Performance Analysis of Real-Time Embeded Software
Scope-Tree: A Program Representation for Symbolic Worst-Case Execution Time Analysis
ECRTS '02 Proceedings of the 14th Euromicro Conference on Real-Time Systems
WCET Analysis of Probabilistic Hard Real-Time Systems
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
Intra-task scenario-aware voltage scheduling
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Automated WCET analysis based on program modes
Proceedings of the 2006 international workshop on Automation of software test
Global memory optimisation for embedded systems allowed by code duplication
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Resource prediction for media stream decoding
Proceedings of the conference on Design, automation and test in Europe
Probabilistic performance risk analysis at system-level
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Scenario selection and prediction for DVS-aware scheduling of multimedia applications
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
System-scenario-based design of dynamic embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamic MIPS rate stabilization in out-of-order processors
Proceedings of the 36th annual international symposium on Computer architecture
Designing heterogeneous embedded network-on-chip platforms with users in mind
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parametric timing analysis and its application to dynamic voltage scaling
ACM Transactions on Embedded Computing Systems (TECS)
Performance model checking scenario-aware dataflow
FORMATS'11 Proceedings of the 9th international conference on Formal modeling and analysis of timed systems
Exploiting media stream similarity for energy-efficient decoding and resource prediction
ACM Transactions on Embedded Computing Systems (TECS)
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Modern embedded applications usually have real-time constraints and they are implemented using heterogeneous multiprocessor systems-on-chip. Dimensioning a system requires accurate estimations of the worst-case execution time (WCET). Overestimation leads to over-dimensioning. This paper introduces a method for automatic discovery of scenarios that incorporate correlations between different parts of applications. It is based on the application parameters with a large impact on the execution time. We show on a benchmark that, using scenarios, the estimated WCET may be reduced with 16%.