Program path analysis to bound cache-related preemption delay in preemptive real-time systems
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Cache-Conscious Limited Preemptive Scheduling
Real-Time Systems
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ACM Transactions on Embedded Computing Systems (TECS)
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RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
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ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
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We propose an enhanced technique for analyzing, and thus bounding cache related preemption delay in fixed priority preemptive scheduling focusing on instruction caching. The proposed technique improves upon previous techniques in two important ways. First, the technique takes into account the relationship between a preempted task and the set of tasks that execute during the preemption when calculating the cache related preemption delay. Second, the technique considers phasing of tasks to eliminate many infeasible task interactions. These two features are expressed as constraints of a linear programming problem whose solution gives a guaranteed upper bound on the cache related preemption delay. The paper also compares the proposed technique with previous techniques. The results show that the proposed technique gives up to 60% tighter prediction of the worst case response time than the previous techniques.