Calculating the maximum, execution time of real-time programs
Real-Time Systems
The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Software-based cache partitioning for real-time applications
Journal of Computer and Software Engineering - Special issue: hardware-software codesign
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling
IEEE Transactions on Computers
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Performance estimation of embedded software with instruction cache modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Performance analysis of embedded software using implicit path enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New directions in compiler technology for embedded systems (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Accurate estimation of cache-related preemption delay
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Multiple process execution in cache related preemption delay analysis
Proceedings of the 4th ACM international conference on Embedded software
Scalable precision cache analysis for preemptive scheduling
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
WCRT analysis for a uniprocessor with a unified prioritized cache
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Timing analysis for preemptive multitasking real-time systems with caches
ACM Transactions on Embedded Computing Systems (TECS)
Cache-aware timing analysis of streaming applications
Real-Time Systems
Scratchpad allocation for concurrent embedded software
ACM Transactions on Programming Languages and Systems (TOPLAS)
Resilience analysis: tightening the CRPD bound for set-associative caches
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Tightening the bounds on feasible preemptions
ACM Transactions on Embedded Computing Systems (TECS)
Cache-related preemption delay via useful cache blocks: Survey and redefinition
Journal of Systems Architecture: the EUROMICRO Journal
A synergetic approach to accurate analysis of cache-related preemption delay
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
Integrated instruction cache analysis and locking in multitasking real-time systems
Proceedings of the 50th Annual Design Automation Conference
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Unpredictable behavior of cache memory males it difficult to statically analyze the worst-case performance of real-time systems. This problem is exacerbated in case of preemptive multitask systems due to intertask cache in terference, called Cache-Related Preemption Delay (CRPD). This paper proposes an approach to analysis of the tight upper bound on CRPD which a task might impose on lower-priority tasks. Our method determines the program execution path of the task which requires the maximum number of cache blocks using an integer linear programming technique. Experimental results show that our approach provides up to 69% tighter bounds on CRPD than a previous approach.