Real-time Euclid: a language for reliable real-time systems
IEEE Transactions on Software Engineering - Special issue on reliability and safety in real-time process control
The 80960 microprocessor architecture
The 80960 microprocessor architecture
Reasoning About Time in Higher-Level Language Software
IEEE Transactions on Software Engineering
Calculating the maximum, execution time of real-time programs
Real-Time Systems
i860 microprocessor family programmer's reference manual
i860 microprocessor family programmer's reference manual
Predicting deterministic execution times of real-time programs
Predicting deterministic execution times of real-time programs
Automated Derivation of Time Bounds in Uniprocessor Concurrent Systems
IEEE Transactions on Software Engineering
Co-synthesis of hardware and software for digital embedded systems
Co-synthesis of hardware and software for digital embedded systems
Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Program path analysis to bound cache-related preemption delay in preemptive real-time systems
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Timing analysis of embedded software for speculative processors
Proceedings of the 15th international symposium on System Synthesis
Scenario-based software characterization as a contingency to traditional program profiling
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Architecture-level performance evaluation of component-based embedded systems
Proceedings of the 40th annual Design Automation Conference
Accurate timing analysis by modeling caches, speculation and their interaction
Proceedings of the 40th annual Design Automation Conference
Compiler optimization-space exploration
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Accurate estimation of cache-related preemption delay
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Application-directed voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Modeling control speculation for timing analysis
Real-Time Systems
Strategies for the integration of hardware and software IP components in embedded systems-on-chip
Integration, the VLSI Journal - Special issue: IP and design reuse
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
WCRT analysis for a uniprocessor with a unified prioritized cache
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Instruction code mapping for performance increase and energy reduction in embedded computer systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling out-of-order processors for WCET analysis
Real-Time Systems
Timing analysis for preemptive multitasking real-time systems with caches
ACM Transactions on Embedded Computing Systems (TECS)
Efficient and scalable compiler-directed energy optimization for realtime applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accounting for cache-related preemption delay in dynamic priority schedulability analysis
Proceedings of the conference on Design, automation and test in Europe
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Applying neural networks to performance estimation of embedded software
Journal of Systems Architecture: the EUROMICRO Journal
Cache modeling in probabilistic execution time analysis
Proceedings of the 45th annual Design Automation Conference
Cache-aware timing analysis of streaming applications
Real-Time Systems
WCET Analysis of Data Dependent, Component Oriented, Embedded Software Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Fast instruction cache modeling for approximate timed HW/SW co-simulation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Recent additions on the application programming interface of the TMO support middleware
Proceedings of the 13th Monterey conference on Composition of embedded systems: scientific and industrial issues
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Timing analysis and timing predictability
FMCO'04 Proceedings of the Third international conference on Formal Methods for Components and Objects
An architectural framework for detecting process hangs/crashes
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Analyzing loop paths for execution time estimation
ICDCIT'05 Proceedings of the Second international conference on Distributed Computing and Internet Technology
Elastic computing: A portable optimization framework for hybrid computers
Parallel Computing
Precise timing analysis for direct-mapped caches
Proceedings of the 50th Annual Design Automation Conference
A Unified WCET analysis framework for multicore platforms
ACM Transactions on Embedded Computing Systems (TECS)
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Embedded systems generally interact in some way with the outside world. This may involve measuring sensors and controlling actuators, communicating with other systems, or interacting with users. These functions impose real-time constraints on system design. Verification of these specifications requires computing an upper bound on the worst-case execution time (WCET) of a hardware/software system. Furthermore, it is critical to derive a tight upper bound on WCET in order to make efficient use of system resources. The problem of bounding WCET is particularly difficult on modern processors. These processors use cache-based memory systems that vary memory access time based on the dynamic memory access pattern of the program. This must be accurately modeled in order to tightly bound WCET. Several analysis methods have been proposed to bound WCET on processors with instruction caches. Existing approaches either search all possible program paths, an intractable problem, or they use highly pessimistic assumptions to limit the search space. In this paper we present a more effective method for modeling instruction cache activity and computing a tight bound on WCET. The method uses an integer linear programming formulation and does not require explicit enumeration of program paths. The method is implemented in the program cinderella and we present some experimental results of this implementation.