Precise timing analysis for direct-mapped caches

Authors:
Sidharta Andalam;Alain Girault;Roopak Sinha;Partha Roop;Jan Reineke
Affiliations:
TUM CREATE, Singapore;INRIA - Grenoble, France;University of Auckland, New Zealand;University of Auckland, New Zealand;Saarland University- Saarbrücken, Germany
Venue:
Proceedings of the 50th Annual Design Automation Conference
Year:
2013

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Abstract

Safety-critical systems require guarantees on their worst-case execution times. This requires modelling of speculative hardware features such as caches that are tailored to improve the average-case performance, while ignoring the worst case, which complicates the Worst Case Execution Time (WCET) analysis problem. Existing approaches that precisely compute WCET suffer from state-space explosion. In this paper, we present a novel cache analysis technique for direct-mapped instruction caches with the same precision as the most precise techniques, while improving analysis time by up to 240 times. This improvement is achieved by analysing individual control points separately, and carrying out optimisations that are not possible with existing techniques.