Performance estimation of embedded software with instruction cache modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast cache and bus power estimation for parameterized system-on-a-chip design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
High level cache simulation for heterogeneous multiprocessors
Proceedings of the 41st annual Design Automation Conference
Cache characterization surfaces and predicting workload miss rates
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems
ESTMED '06 Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
Automatic instrumentation of embedded software for high level hardware/software co-simulation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Exact and fast L1 cache simulation for embedded systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast data-cache modeling for native co-simulation
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fast and accurate source-level simulation of software timing considering complex code optimizations
Proceedings of the 48th Design Automation Conference
Dominator homomorphism based code matching for source-level simulation of embedded software
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hybrid source-level simulation of data caches using abstract cache models
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
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Approximate timed co-simulation has been proposed as a fast solution for system modeling in early design steps. This co-simulation technique enables the simulation of systems at speeds close to functional execution, while considering timing effects. As a consequence, system performance estimations can be obtained early, enabling efficient design space exploration and system refinement. To achieve fast simulation speeds, first the SW code is pre-annotated with time information and then it is natively executed, performing what is called native-based co-simulation. To obtain sufficiently accurate performance estimations, the effect of the system components must be considered. Among them, processor caches are really important, as they have a strong impact on the overall system performance. However, no efficient techniques for cache modeling in native-based co-simulation have been proposed. Previous works considering caches apply slow cache models based on tag search, similar to ISS-based models. This solution slows down the simulation speed, greatly reducing the efficiency of native based co-simulations. In this paper, a high-level instruction cache model is proposed, along with the required instrumentation for native simulation. This model allows the designer to obtain cache hit/miss rate estimations with simulation speeds very close to native execution. Results present a speed-up of two orders of magnitude with respect to ISS and one order of magnitude regarding previous approaches in native simulation. Miss rate estimation error remains below 5%.