Fast instruction cache modeling for approximate timed HW/SW co-simulation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Fast data-cache modeling for native co-simulation
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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The design exploration procedure of DSP systems using simulation tools is a time-consuming process, even for low complexity applications. The main goal of the design methodology introduced in this paper is to provide fast and accurate estimates of the number of (-micro) instructions and the instruction cache miss rate of DSP applications implemented on a programmable embedded platform, during the early design phases. Specific information is extracted from both the high-level code description (C code) of the DSP application considered and its corresponding assembly code, without carrying out any kind of simulation. The proposed methodology requires only a single execution of the application in a general-purpose processor and uses only the assembly code of the targeted embedded processor. In order to automate the estimation procedure, a new software tool, which implements the proposed methodology, has been developed. Using nine real-life applications from different domains of the DSP field, it has been proved that with the proposed methodology the number of instructions and the miss rate of instruction cache can be estimated with high accuracy (95%). Furthermore, the required time cost is much smaller (orders of magnitude) than the simulation-based approaches