High level cache simulation for heterogeneous multiprocessors
Proceedings of the 41st annual Design Automation Conference
Measuring Benchmark Similarity Using Inherent Program Characteristics
IEEE Transactions on Computers
Accurate memory signatures and synthetic address traces for HPC applications
Proceedings of the 22nd annual international conference on Supercomputing
Fast instruction cache modeling for approximate timed HW/SW co-simulation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Fast data-cache modeling for native co-simulation
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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In this paper, we use locality surfaces to predict cache miss rates. To do this, we introduce two new surfaces. The miss surface characterizes how a trace is filtered by a particular cache in terms of locality. A cache characterization surface helps us examine caches in terms of what stride/delay relationships are likely to cause misses in the cache. The cache characterization surface is independent of any workload. We use these surfaces to quantitatively predict cache miss rates with some degree of accuracy.