Reliable estimation of execution time of embedded software
Proceedings of the conference on Design, automation and test in Europe
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
Proceedings of the conference on Design, automation and test in Europe
RTOS scheduling in transaction level models
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
System-Level Performance Analysis in SystemC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Generic RTOS Model for Real-time Systems Simulation with SystemC
Proceedings of the conference on Design, automation and test in Europe - Volume 3
LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Retargetable profiling for rapid, early system-level design space exploration
Proceedings of the 41st annual Design Automation Conference
High level cache simulation for heterogeneous multiprocessors
Proceedings of the 41st annual Design Automation Conference
Intermediate-representation recovery from low-level code
Proceedings of the 2006 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Cycle-approximate retargetable performance estimation at the transaction level
Proceedings of the conference on Design, automation and test in Europe
TotalProf: a fast and accurate retargetable source code profiler
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Native MPSoC co-simulation environment for software performance estimation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Fast instruction cache modeling for approximate timed HW/SW co-simulation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
TLM+ modeling of embedded HW/SW systems
Proceedings of the Conference on Design, Automation and Test in Europe
RTOS-aware refinement for TLM2.0-based HW/SW designs
Proceedings of the Conference on Design, Automation and Test in Europe
Fast data-cache modeling for native co-simulation
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fast and accurate source-level simulation of software timing considering complex code optimizations
Proceedings of the 48th Design Automation Conference
Dominator homomorphism based code matching for source-level simulation of embedded software
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Combined WCET analysis of bitcode and machine code using control-flow relation graphs
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Hybrid source-level simulation of data caches using abstract cache models
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Accurate source-level simulation of embedded software with respect to compiler optimizations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Automated, retargetable back-annotation for host compiled performance and power modeling
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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We propose an automatic instrumentation method for embedded software annotation to enable performance modeling in high level hardware/software co-simulation environments. The proposed "cross-annotation" technique consists of extending a retargetable compiler infrastructure to allow the automatic instrumentation of embedded software at the basic block level. Thus, target and annotated native binaries are guaranteed to have isomorphic control flow graphs (CFG). The proposed method takes into account the processor-specific optimizations at the compiler level and proves to be accurate with low simulation overhead.