Calculating the maximum, execution time of real-time programs
Real-Time Systems
Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Rate analysis for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Static timing analysis of embedded software on advanced processor architectures
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Reliable estimation of execution time of embedded software
Proceedings of the conference on Design, automation and test in Europe
Source-level execution time estimation of C programs
Proceedings of the ninth international symposium on Hardware/software codesign
Performance analysis with confidence intervals for embedded software processes
Proceedings of the 14th international symposium on Systems synthesis
Timed compiled-code simulation of embedded software for performance analysis of SOC design
Proceedings of the 39th annual Design Automation Conference
System Design with SystemC
Behavioral Intervals in Embedded Software: Timing and Power Analysis of Embedded Real-Time Software Processes
Scheduling for Embedded Real-Time Systems
IEEE Design & Test
Platform-Based Design and Software Design Methodology for Embedded Systems
IEEE Design & Test
Proceedings of the 40th annual Design Automation Conference
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
Proceedings of the conference on Design, automation and test in Europe
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Systemic Embedded Software Generation from SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A framework for heterogeneous specification and design of electronic embedded systems in SystemC
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient design methods for embedded communication systems
EURASIP Journal on Embedded Systems
RRES: a novel approach to the partitioning problem for a typical subset of system graphs
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
Automatic instrumentation of embedded software for high level hardware/software co-simulation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Native MPSoC co-simulation environment for software performance estimation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
RTOS-aware refinement for TLM2.0-based HW/SW designs
Proceedings of the Conference on Design, Automation and Test in Europe
Source-level timing annotation for fast and accurate TLM computation model generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Performance analysis techniques for multi-soft-core and many-soft-core systems
International Journal of Reconfigurable Computing
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As both the ITRS and the Medea+ DA Roadmaps have highlighted, early performance estimation is an essential step in any SoC design methodology [1-2]. This paper presents a C++ library for timing estimation at system level. The library is based on a general and systematic methodology that takes as input the original SystemC source code without anymodification and provides the estimation parameters by simply including the library within a usual simulation. As a consequence, the same models of computation used during system design are preserved and all simulation conditions are maintained. The method exploits the advantages of dynamic analysis, that is, easy management of unpredictable data-dependentconditions and computational efficiency compared with other alternatives (ISS or RT simulation, without the need for SW generation and compilation and HW synthesis). Results obtained on several examples show the accuracy of the method. In addition to the fundamental parameters needed for system-level design exploration, the proposed methodology allows the designer to include capture points at any place in the code. The user can process the corresponding captured events for unrestricted timing constraint verification.