Embedded software development on top of transaction-level models
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Efficient implementation of native software simulation for MPSoC
Proceedings of the conference on Design, automation and test in Europe
Automatic instrumentation of embedded software for high level hardware/software co-simulation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
White box performance analysis considering static non-preemptive software scheduling
Proceedings of the Conference on Design, Automation and Test in Europe
OveRSoC: a framework for the exploration of RTOS for RSoC platforms
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
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At high abstraction level, multi-processor system-on-chip (SoC) designs are specified as assembling of IP's which can be hardware or software. The refinement of communication between these different IP's, known as hardware/software interfaces, is widely seen as the design bottleneck due to their complexity. In order to perform early design validation and architecture exploration, flexible executable models of these interfaces are needed at different abstraction levels. In this paper, we define a unified methodology to implement executable models of the hardware/software interface based on SystemC. The proposed formalism based on the concept of services gives to this approach the flexibility needed for architecture exploration and the ability to be used in automatic generation tools. A case study of hardware/software interface modeling at the transaction accurate level is presented. Experimental results show that this method allows higher simulation speed with early performance estimation.