Alternative implementations of two-level adaptive branch prediction
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A worst case timing analysis technique for instruction prefetch buffers
Selected papers of the short notes session on Euromicro '94
Wrong-path instruction prefetching
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Performance estimation of embedded software with instruction cache modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Worst Case Execution Time Analysis for a Processor withBranch Prediction
Real-Time Systems - Special issue on worst-case execution-time analysis
Retargetable static timing analysis for embedded software
Proceedings of the 14th international symposium on Systems synthesis
Associative caches in formal software timing analysis
Proceedings of the 39th annual Design Automation Conference
Timing analysis of embedded software for speculative processors
Proceedings of the 15th international symposium on System Synthesis
Mispredicted Path Cache Effects
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Processor Pipelines and Their Properties for Static WCET Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Bounding Loop Iterations for Timing Analysis
RTAS '98 Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium
Accurate estimation of cache-related preemption delay
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Accurate software performance estimation using domain classification and neural networks
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Modeling control speculation for timing analysis
Real-Time Systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Applying neural networks to performance estimation of embedded software
Journal of Systems Architecture: the EUROMICRO Journal
Cache-aware timing analysis of streaming applications
Real-Time Systems
Predicated Worst-Case Execution-Time Analysis
Ada-Europe '09 Proceedings of the 14th Ada-Europe International Conference on Reliable Software Technologies
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Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysis, but also modeling the effects of complex micro-architectural features in modern processors. Speculative execution and caching are very common in current processors. Hence one needs to model the effects of these features on the Worst Case Execution Time (WCET) of a program. Even though the individual effects of these features have been studied recently, their combined effects have not been investigated. We do so in this paper. This is a non-trivial task because speculative execution can indirectly affect cache performance (e.g., speculatively executed blocks can cause additional cache misses). Our technique starts from the control flow graph of the embedded program, and uses integer linear programming to estimate the program's WCET. The accuracy of our modeling is illustrated by tight estimates obtained on realistic benchmarks.