Reasoning About Time in Higher-Level Language Software
IEEE Transactions on Software Engineering
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Alternative implementations of two-level adaptive branch prediction
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Pipeline behavior prediction for superscalar processors by abstract interpretation
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Performance estimation of embedded software with instruction cache modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Worst Case Execution Time Analysis for a Processor withBranch Prediction
Real-Time Systems - Special issue on worst-case execution-time analysis
Retargetable static timing analysis for embedded software
Proceedings of the 14th international symposium on Systems synthesis
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Bounding Loop Iterations for Timing Analysis
RTAS '98 Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium
A Worst Case Timing Analysis Technique for Multiple-Issue Machines
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Accurate timing analysis by modeling caches, speculation and their interaction
Proceedings of the 40th annual Design Automation Conference
Modeling control speculation for timing analysis
Real-Time Systems
Chronos: A timing analyzer for embedded software
Science of Computer Programming
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Source-level timing annotation for fast and accurate TLM computation model generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Static timing analysis of embedded software is important for systems with hard real-time constraints. To accurately estimate time bounds, it is essential to model the underlying micro architecture. In this paper, we study static timing analysis of embedded programs for modern processors with speculative execution. Speculation of conditional branch outcomes significantly improves processor performance, and hence program execution time. Although speculation is used in most modern processors, its effect on software timing has not been systematically studied before. The main contribution of our work is a parameterized framework to model different control flow speculation schemes. The accuracy of our framework is illustrated through tight timing estimates obtained for benchmark programs.