Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Embedded program timing analysis based on path clustering and architecture classification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Static timing analysis of embedded software on advanced processor architectures
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Intervals in software execution cost analysis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Performance Analysis of Real-Time Embeded Software
Performance Analysis of Real-Time Embeded Software
Behavioral Intervals in Embedded Software: Timing and Power Analysis of Embedded Real-Time Software Processes
Data flow based cache prediction using local simulation
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Efficient worst case timing analysis of data caching
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Accurate timing analysis by modeling caches, speculation and their interaction
Proceedings of the 40th annual Design Automation Conference
Accurate estimation of cache-related preemption delay
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Modeling control speculation for timing analysis
Real-Time Systems
Timing analysis for preemptive multitasking real-time systems with caches
ACM Transactions on Embedded Computing Systems (TECS)
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Precise cache analysis is crucial to formally determine program running time. As cache simulation is unsafe with respect to the conservative running time bounds for real-time systems, current cache analysis techniques combine basic block level cache modeling with explicit or implicit program path analysis. We present an approach that extends instruction and data cache modeling from the granularity of basic blocks to program segments thereby increasing the overall running time analysis precision. Data flow analysis and local simulation of program segments are combined to safely predict cache line contents for associative caches in software running time analysis. The experiments show significant improvements in analysis precision over previous approaches on a typical embedded processor.