Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Predictable cache design for real-time systems
Predictable cache design for real-time systems
Predicting deterministic execution times of real-time programs
Predicting deterministic execution times of real-time programs
Software estimation from executable specifications
Journal of Computer and Software Engineering - Special issue: hardware-software codesign
Performance estimation of embedded software with instruction cache modeling
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast Simulation of Computer Architectures
Fast Simulation of Computer Architectures
Combining multiple models of computation for scheduling and allocation
Proceedings of the 6th international workshop on Hardware/software codesign
Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder
Proceedings of the 6th international workshop on Hardware/software codesign
Software timing analysis using HW/SW cosimulation and instruction set simulator
Proceedings of the 6th international workshop on Hardware/software codesign
A case study on modeling shared memory access effects during performance analysis of HW/SW systems
Proceedings of the 6th international workshop on Hardware/software codesign
A compilation-based software estimation scheme for hardware/software co-simulation
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Power conscious fixed priority scheduling for hard real-time systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Software performance estimation strategies in a system-level design tool
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Fast performance analysis of bus-based system-on-chip communication architectures
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Static timing analysis of embedded software on advanced processor architectures
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Intervals in software execution cost analysis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Path clustering in software timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Associative caches in formal software timing analysis
Proceedings of the 39th annual Design Automation Conference
Codesign of embedded systems: status and trends
Readings in hardware/software co-design
Codesign of Embedded Systems: Status and Trends
IEEE Design & Test
IEEE Transactions on Software Engineering
Power management points in power-aware real-time systems
Power aware computing
An Integrated Approach for Applying Dynamic Voltage Scaling to Hard Real-Time Systems
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
Predictive Strategies for Low-Power RTOS Scheduling
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
IEEE Transactions on Parallel and Distributed Systems
Maximizing rewards for real-time applications with energy constraints
ACM Transactions on Embedded Computing Systems (TECS)
Application-directed voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems
IEEE Transactions on Computers
Power-Aware Scheduling for Periodic Real-Time Tasks
IEEE Transactions on Computers
Maximizing the system value while satisfying time and energy constraints
IBM Journal of Research and Development
Power-Aware Scheduling for AND/OR Graphs in Real-Time Systems
IEEE Transactions on Parallel and Distributed Systems
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Context Sensitive Performance Analysis of Automotive Applications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Minimizing expected energy in real-time embedded systems
Proceedings of the 5th ACM international conference on Embedded software
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM SIGBED Review - Special issue: The work-in-progress (WIP) session of the RTSS 2005
SoCDAL: System-on-chip design AcceLerator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimizing expected energy consumption in real-time systems through dynamic voltage scaling
ACM Transactions on Computer Systems (TOCS)
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
DVSMT: Dynamic Voltage Scaling for Scheduling Mixed Real-Time Tasks
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems
Proceedings of the 47th Design Automation Conference
Transition-aware DVS algorithm for real-time systems using tree structure analysis
Journal of Systems Architecture: the EUROMICRO Journal
Reliability-aware dynamic energy management in dependable embedded real-time systems
ACM Transactions on Embedded Computing Systems (TECS)
Source-level timing annotation for fast and accurate TLM computation model generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Quasi-static voltage scaling for energy minimization with time constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic voltage scaling for real-time scheduling of multimedia tasks
PCM'05 Proceedings of the 6th Pacific-Rim conference on Advances in Multimedia Information Processing - Volume Part II
Energy management for embedded multithreaded processors with integrated EDF scheduling
ARCS'05 Proceedings of the 18th international conference on Architecture of Computing Systems conference on Systems Aspects in Organic and Pervasive Computing
Encore: low-cost, fine-grained transient fault recovery
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Journal of Computer and System Sciences
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Formal Program running time verification is an important issue in system design required for performance optimization under "first-time-right" design constraints and for real-time system verification. Simulation based approaches or simple instruction counting are not appropriate and risky for more complex architectures in particular with data dependent execution paths. Formal analysis techniques have suffered from loose timing bounds leading to significant performance penalties when strictly adhered to. We present an approach which combines simulation and formal techniques in a safe way to improve analysis precision and tighten the timing bounds. Using a set of processor parameters, it is adaptable to arbitrary processor architectures. The results show an unprecedented analysis precision allowing to reduce performance overhead for provably correct system or interface timing.