Computer Networks and ISDN Systems
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient software performance estimation methods for hardware/software codesign
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Principles of digital design
A dynamic design estimation and exploration environment
DAC '97 Proceedings of the 34th annual Design Automation Conference
A hardware/software partitioner using a dynamically determined granularity
DAC '97 Proceedings of the 34th annual Design Automation Conference
Embedded program timing analysis based on path clustering and architecture classification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
System-level exploration with SpecSyn
DAC '98 Proceedings of the 35th annual Design Automation Conference
Communication estimation for hardware/software codesign
Proceedings of the 6th international workshop on Hardware/software codesign
Software timing analysis using HW/SW cosimulation and instruction set simulator
Proceedings of the 6th international workshop on Hardware/software codesign
Fast hardware-software co-simulation using VHDL models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
MCI—multilanguage distributed co-simulation tool
DIPES '98 Proceedings of the IFIP WG10.3/WG10.5 international workshop on Distributed and parallel embedded systems
Multilanguage specification for system design
System-level synthesis
Performance estimation for real-time distributed embedded systems
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A Methodology for Rapid Analysis and Optimization of Embedded Systems
ECBS '96 Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems
Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
An approach to the adaptation of estimated cost parameters in the COSYMA system
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
System-level design space exploration for security processor prototyping in analytical approaches
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC
IEEE Transactions on Computers
Ad-hoc HW/SW architectures for DBMSs: a co-design approach
AIKED'07 Proceedings of the 6th Conference on 6th WSEAS Int. Conf. on Artificial Intelligence, Knowledge Engineering and Data Bases - Volume 6
Communication architecture simulation on the virtual synchronization framework
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
PAM-SoC: a toolchain for predicting MPSoC performance
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
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This paper addresses performance estimation and architecture exploration issues within the context of hardware/software codesign. We introduce a new methodology to rapidly explore the large design space encountered in hardware/software systems. The proposed methodology is based on a fast and accurate estimation approach. This estimation approach takes advantage of both system and RT levels of abstraction, and combines both static and dynamic analysis techniques, in order to obtain the best trade-off between speed and accuracy. It has been implemented as an extension to a hardware/software codesign flow to enable the exploration of a large number of multiprocessor architecture solutions from the very start of the design process. The effectiveness of the proposed methodology is illustrated by a significant application example. Experimental results indicate strong advantages of the proposed methodology.