Reasoning About Time in Higher-Level Language Software
IEEE Transactions on Software Engineering
Calculating the maximum, execution time of real-time programs
Real-Time Systems
A Multiframe Model for Real-Time Tasks
IEEE Transactions on Software Engineering
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling
IEEE Transactions on Computers
Performance estimation of embedded software with instruction cache modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Real-Time Systems
Program path analysis to bound cache-related preemption delay in preemptive real-time systems
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Model composition for scheduling analysis in platform design
Proceedings of the 39th annual Design Automation Conference
System level design with spade: an M-JPEG case study
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A stream compiler for communication-exposed architectures
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Dynamic- and Static-priority Scheduling of Recurring Real-time Tasks
Real-Time Systems
A Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IEEE Design & Test
Imagine: Media Processing with Streams
IEEE Micro
A Dynamic Programming Algorithm for Cache Memory Partitioning for Real-Time Systems
IEEE Transactions on Computers
StreamIt: A Language for Streaming Applications
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
Accurate timing analysis by modeling caches, speculation and their interaction
Proceedings of the 40th annual Design Automation Conference
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
Low-Complexity Algorithms for Static Cache Locking in Multitasking Hard Real-Time Systems
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Event Model Interfaces for Heterogeneous System Analysis
Proceedings of the conference on Design, automation and test in Europe
Accurate estimation of cache-related preemption delay
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Scheduling Analysis Integration for Heterogeneous Multiprocessor SoC
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Data Caches in Multitasking Hard Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Context-Aware Performance Analysis for Efficient Embedded System Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Rate analysis for streaming applications with on-chip buffer constraints
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Multiple process execution in cache related preemption delay analysis
Proceedings of the 4th ACM international conference on Embedded software
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Modeling Out-of-Order Processors for Software Timing Analysis
RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
Abstracting functionality for modular performance analysis of hard real-time systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
Logic of constraints: a quantitative performance and functional constraint formalism
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Instruction cache locking for multi-task real-time embedded systems
Real-Time Systems
Instruction Cache Locking for Embedded Systems using Probability Profile
Journal of Signal Processing Systems
Hi-index | 0.00 |
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. Such applications process potentially infinite streams of audio/video data or network packets and are found in a wide range of devices, starting from mobile phones to set-top boxes. Given a streaming application and an architecture, the timing analysis problem is to determine the timing properties of the processed data stream, given the timing properties of the input stream. This problem arises while determining many common performance metrics related to streaming applications and the mapping of such applications onto hardware architectures. Such metrics include the maximum delay experienced by any data item of the stream and the maximum backlog or the buffer requirement to store the incoming stream. Most of the previous work related to estimating or optimizing these metrics take a high-level view of the architecture and neglect micro-architectural features such as caches. In this paper, we show that an accurate estimation of these metrics, however, heavily relies on an appropriate modeling of the processor micro-architecture. Towards this, we present a novel framework for cache-aware timing analysis of stream processing applications. Our framework accurately models the evolution of the instruction cache of the underlying processor as a stream is processed, and the fact that the execution time involved in processing any data item depends on all the previous data items occurring in the stream. The main contribution of our method lies in its ability to seamlessly integrate program analysis techniques for micro-architectural modeling with known analytical methods for analyzing streaming applications, which treat the arrival/service of event streams as mathematical functions. This combination is powerful as it allows to model the code/cache-behavior of the streaming application, as well as the manner in which it is triggered by event arrivals. We employ our analysis method to an MPEG-2 encoder application and our experiments indicate that detailed modeling of the cache behavior is efficient, scalable and leads to more accurate timing/buffer size estimates.