Scheduling Analysis Integration for Heterogeneous Multiprocessor SoC

  • Authors:
  • Kai Richter;Razvan Racu;Rolf Ernst

  • Affiliations:
  • -;-;-

  • Venue:
  • RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
  • Year:
  • 2003

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Abstract

Today, only very few techniques out of the host of work on formalperformance and timing analysis have been adopted in MpSoC(multiprocessor system-on-chip) design. One of the key reasons isa mismatch between the scheduling models assumed in most formalapproaches and the heterogenous world of MpSoC schedulingtechniques and communication patterns. This heterogeneity resultsfrom IP reuse and a plug-and-play design style, required to effectivelyreach the necessary design productivity. A second problem isthe model complexity. While complex, specialized models can findtheir way into industry niches, their broad acceptance is extremelydoubtful. In this paper, we review the existing scheduling analysistechniques with respect to these key requirements and derive a goodcompromise between model simplicity on the one hand, and applicabilityto MpSoC design on the other hand. The approach representssystem-level scheduling analysis as a flow-analysis problemfor event streams that can be configured to reuse the existing localscheduling analysis techniques. We define transformations betweenfew key event stream models to meet the interfacing requirements ofthe compositional design style. An example demonstrates the applicationof the approach, as well as the worthiness of the results.