An extendible approach for analyzing fixed priority hard real-time tasks
Real-Time Systems
Holistic schedulability analysis for distributed hard real-time systems
Microprocessing and Microprogramming - Parallel processing in embedded real-time systems
A Multiframe Model for Real-Time Tasks
IEEE Transactions on Software Engineering
Bounding Cache-Related Preemption Delay for Real-Time Systems
IEEE Transactions on Software Engineering
PowerPC 603, A Microprocessor for Portable Computers
IEEE Design & Test
StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Schedulability Analysis for Tasks with Static and Dynamic Offsets
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
The ARM9 Family - High Performance Microprocessors for Embedded Applications
ICCD '98 Proceedings of the International Conference on Computer Design
MAST: Modeling and Analysis Suite for Real Time Applications
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
Scheduling Analysis Integration for Heterogeneous Multiprocessor SoC
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Bounding Worst-Case Access Times in Modern Multiprocessor Systems
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
Extended Analysis with Reduced Pessimism for Systems with Limited Parallelism
RTCSA '05 Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
An Interface Algebra for Real-Time Components
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
Timing Analysis of the FlexRay Communication Protocol
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
Integrated analysis of communicating tasks in MPSoCs
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Scalable precision cache analysis for real-time software
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Response-Time Analysis for Globally Scheduled Symmetric Multiprocessor Platforms
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Obstacles in Worst-Case Execution Time Analysis
ISORC '08 Proceedings of the 2008 11th IEEE Symposium on Object Oriented Real-Time Distributed Computing
Real-Time Synchronization on Multiprocessors: To Block or Not to Block, to Suspend or Spin?
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
Reliable performance analysis of a multicore multithreaded system-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Providing accurate event models for the analysis of heterogeneous multiprocessor systems
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A New Notion of Useful Cache Block to Improve the Bounds of Cache-Related Preemption Delay
ECRTS '09 Proceedings of the 2009 21st Euromicro Conference on Real-Time Systems
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A predictable simultaneous multithreading scheme for hard real-time
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
Bounding the shared resource load for the performance analysis of multiprocessor systems
Proceedings of the Conference on Design, Automation and Test in Europe
Timed automata based analysis of embedded system architectures
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Power monitoring for mixed-criticality on a many-core platform
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Multi-core composability in the face of memory-bus contention
ACM SIGBED Review
| Hi-index | 0.00 |
Predicting timing behavior is key to reliable real-time system design and verification, but becomes increasingly difficult for current multiprocessor systems on chip. The integration of formerly separate functionality into a single multicore system introduces new intercore timing dependencies resulting from the common use of the now shared resources. This feedback of system timing on local timing makes traditional performance analysis approaches inappropriate. This article presents a general methodology to model the shared resource traffic and consider its effect on the local task execution. The aggregate busy time captures the timing of multiple accesses to a shared memory far better than the traditional models that focus on the timing of individual events. An iterative approach is proposed to tackle the analysis dependencies that exist in systems with event-driven task activation and dynamic resource arbitration.