Knapsack problems: algorithms and computer implementations
Knapsack problems: algorithms and computer implementations
Bounding Cache-Related Preemption Delay for Real-Time Systems
IEEE Transactions on Software Engineering
StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
Scalable precision cache analysis for real-time software
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Obstacles in Worst-Case Execution Time Analysis
ISORC '08 Proceedings of the 2008 11th IEEE Symposium on Object Oriented Real-Time Distributed Computing
Convergent Lagrangian and domain cut method for nonlinear knapsack problems
Computational Optimization and Applications
A New Notion of Useful Cache Block to Improve the Bounds of Cache-Related Preemption Delay
ECRTS '09 Proceedings of the 2009 21st Euromicro Conference on Real-Time Systems
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Real-time performance analysis of multiprocessor systems with shared memory
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the tenth ACM international conference on Embedded software
Memory-centric scheduling for multicore hard real-time systems
Real-Time Systems
Multi-core composability in the face of memory-bus contention
ACM SIGBED Review
Scheduling of mixed-criticality applications on resource-sharing multicore systems
Proceedings of the Eleventh ACM International Conference on Embedded Software
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
NoC contention analysis using a branch-and-prune algorithm
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Predicting timing behavior is key to reliable real-time system design and verification, but becomes increasingly difficult for current multiprocessor systems on chip. The integration of formerly separate functionality into a single multicore system introduces new inter-core timing dependencies, resulting from the common use of the now shared resources. In order to conservatively bound the delay due to the shared resource accesses, upper bounds on the potential amount of conflicting requests from other processors are required. This paper proposes a method that captures the request distances of multiple shared resource accesses by single tasks and also by multiple tasks that are dynamically scheduled on the same processor. Unlike previous work, we acknowledge the fact that on a single processor, tasks will not actually execute in parallel, but in alternation. This consideration leads to a more accurate load model. In a final step, the approach is extended to allow addressing also dynamic cache misses that do not occur at predefined times but surface dynamically during the execution of the tasks.