Automata For Modeling Real-Time Systems
ICALP '90 Proceedings of the 17th International Colloquium on Automata, Languages and Programming
Lectures on Embedded Systems, European Educational Forum, School on Embedded Systems
Nordic Journal of Computing
Timing analysis of the FlexRay communication protocol
Real-Time Systems
Coscheduling of CPU and I/O Transactions in COTS-Based Embedded Systems
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance analysis of FlexRay-based systems using real-time calculus, revisited
Proceedings of the 2010 ACM Symposium on Applied Computing
Timing Analysis for TDMA Arbitration in Resource Sharing Systems
RTAS '10 Proceedings of the 2010 16th IEEE Real-Time and Embedded Technology and Applications Symposium
Worst-case response time analysis of resource access models in multi-core systems
Proceedings of the 47th Design Automation Conference
Worst case delay analysis for memory interference in multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
Bounding the shared resource load for the performance analysis of multiprocessor systems
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Time and memory tradeoffs in the implementation of AUTOSAR components
Proceedings of the Conference on Design, Automation and Test in Europe
Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software
RTSS '10 Proceedings of the 2010 31st IEEE Real-Time Systems Symposium
Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters
RTAS '11 Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
A Predictable Execution Model for COTS-Based Embedded Systems
RTAS '11 Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking
Proceedings of the Conference on Design, Automation and Test in Europe
The autonomic operating system research project: achievements and future directions
Proceedings of the 50th Annual Design Automation Conference
Diversely enumerating system-level architectures
Proceedings of the Eleventh ACM International Conference on Embedded Software
Scheduling of mixed-criticality applications on resource-sharing multicore systems
Proceedings of the Eleventh ACM International Conference on Embedded Software
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Multicore architectures are increasingly used nowadays in embedded real-time systems. Parallel execution of tasks feigns the possibility of a massive increase in performance. However, this is usually not achieved because of contention on shared resources. Concurrently executing tasks mutually block their accesses to the shared resource, causing non-deterministic delays. Timing analysis of tasks in such systems is then far from trivial. Recently, several analytic methods have been proposed for this purpose, however, they cannot model complex arbitration schemes such as FlexRay which is a common bus arbitration protocol in the automotive industry. This paper considers real-time tasks composed of superblocks, i.e., sequences of computation and resource accessing phases. Resource accesses such as accesses to memories and caches are synchronous, i.e., they cause execution on the processing core to stall until the access is served. For such systems, the paper presents a state-based modeling and analysis approach based on Timed Automata which can model accurately arbitration schemes of any complexity. Based on it, we compute safe bounds on the worst-case response times of tasks. The scalability of the approach is increased significantly by abstracting several cores and their tasks with one arrival curve, which represents their resource accesses and computation times. This curve is then incorporated into the Timed Automata model of the system. The accuracy and scalability of the approach are evaluated with a real-world application from the automotive industry and benchmark applications.