RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Reliable performance analysis of a multicore multithreaded system-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Coscheduling of CPU and I/O Transactions in COTS-Based Embedded Systems
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing Analysis for TDMA Arbitration in Resource Sharing Systems
RTAS '10 Proceedings of the 2010 16th IEEE Real-Time and Embedded Technology and Applications Symposium
Worst case delay analysis for memory interference in multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the tenth ACM international conference on Embedded software
Multi-core composability in the face of memory-bus contention
ACM SIGBED Review
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Multi-processor and multi-core systems are becoming increasingly important in time critical systems. Shared resources, such as shared memory or communication buses are used to share data and read sensors. We consider real-time tasks constituted by superblocks, which can be executed sequentially or by a time triggered static schedule. Three models to access shared resources are explored: (1) the dedicated access model, in which accesses happen only in dedicated phases, (2) the general access model, in which accesses could happen at anytime, and (3) the hybrid access model, combining the dedicated and general access model. For resource access based on a Time Division Multiple Access (TDMA) protocol, we analyze the worst-case completion time for a superblock, derive worst-case response times for tasks and obtain the relation of schedulability between different models. We conclude with proposing the dedicated sequential model as the model of choice for time critical resource sharing multi-processor/multi-core systems.