Holistic schedulability analysis for distributed hard real-time systems
Microprocessing and Microprogramming - Parallel processing in embedded real-time systems
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Hardware-Software Co-Synthesis of Distributed Embedded Systems
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IEEE Design & Test
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IEEE Transactions on Software Engineering
Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
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RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
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WPDRTS '95 Proceedings of the 3rd Workshop on Parallel and Distributed Real-Time Systems
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Proceedings of the conference on Design, automation and test in Europe - Volume 2
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Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Schedulability-driven frame packing for multicluster distributed embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Performance analysis of greedy shapers in real-time systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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ACM Transactions on Embedded Computing Systems (TECS)
Embedded Systems Design
On the use of greedy shapers in real-time embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
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We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.