A Unified WCET analysis framework for multicore platforms

Authors:
Sudipta Chattopadhyay;Lee Kee Chong;Abhik Roychoudhury;Timon Kelter;Peter Marwedel;Heiko Falk
Affiliations:
National University of Singapore, Singapore;National University of Singapore, Singapore;National University of Singapore, Singapore;Technical University of Dortmund, Dortmund, Germany;Technical University of Dortmund;Ulm University, Ulm, Germany
Venue:
ACM Transactions on Embedded Computing Systems (TECS)
Year:
2014

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Abstract

With the advent of multicore architectures, worst-case execution time (WCET) analysis has become an increasingly difficult problem. In this article, we propose a unified WCET analysis framework for multicore processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic microarchitectural components (e.g., pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multicore architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.