WCET driven design space exploration of an object cache
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
Branch target buffers: WCET analysis framework and timing predictability
Journal of Systems Architecture: the EUROMICRO Journal
CIPARSim: cache intersection property assisted rapid single-pass FIFO cache simulation technique
Proceedings of the International Conference on Computer-Aided Design
Worst-case execution time analysis-driven object cache design
Concurrency and Computation: Practice & Experience
FIFO cache analysis for WCET estimation: a quantitative approach
Proceedings of the Conference on Design, Automation and Test in Europe
A Unified WCET analysis framework for multicore platforms
ACM Transactions on Embedded Computing Systems (TECS)
WCET analysis with MRU cache: Challenging LRU for predictability
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |
Schedulability analysis for hard real-time systems requires bounds on the execution times of its tasks. To obtain useful bounds in the presence of caches, static timing analyses must predict cache hits and misses with high precision. For caches with least-recently-used (LRU) replacement policy, precise and efficient cache analyses exist. However, other widely used policies like first-in first-out (FIFO) are inherently harder to analyze. The main contributions of this paper are precise and efficient must- and may-analyses of FIFO based on the novel concept of static phase detection. The analyses statically partition sequences of memory accesses as they will occur during program execution into phases. If subsequent phases contain accesses to the same (similar) set of memory blocks, each phase contributes a bit to the overall goal of predicting hits (misses). The new must-analysis is significantly more precise than prior analyses. Both analyses can be implemented space-efficiently by sharing information using abstract LRU-stacks.