Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Computing Maximum Task Execution Times — A Graph-BasedApproach
Real-Time Systems
On Predicting Data Cache Behavior for Real-Time Systems
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
An object-aware memory architecture
Science of Computer Programming - Special issue on five perspectives on modern memory management: Systems, hardware and theory
jamuth: an IP processor core for embedded Java real-time systems
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
A Java processor architecture for embedded real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
Time-predictable Cache Organization
STFSSD '09 Proceedings of the 2009 Software Technologies for Future Dependable Distributed Systems
Real-Time Java Programming: With Java RTS
Real-Time Java Programming: With Java RTS
Data caching, garbage collection, and the Java memory model
Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems
Towards Time-Predictable Data Caches for Chip-Multiprocessors
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
Worst-case execution time analysis for a Java processor
Software—Practice & Experience
Precise and Efficient FIFO-Replacement Analysis Based on Static Phase Detection
ECRTS '10 Proceedings of the 2010 22nd Euromicro Conference on Real-Time Systems
The embedded Java benchmark suite JemBench
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
Worst-case execution time analysis-driven object cache design
Concurrency and Computation: Practice & Experience
Increasing the efficiency of an embedded multi-core bytecode processor using an object cache
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
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In order to guarantee that real-time systems meet their timing specification, static execution time bounds need to be calculated. Not considering execution time predictability led to architectures which perform well in the average case, but require very pessimistic assumptions when bounding the worst-case execution time (WCET). Computer architecture design is driven by simulations of standard benchmarks estimating the expected average case performance. The design decisions derived from this design methodology do not necessarily result in a WCET analysis-friendly design. Aiming for a time-predictable computer architecture, we propose to employ WCET analysis techniques for the design space exploration of processor architectures. We exemplify this approach by a WCET driven design of a cache for heap allocated objects. Depending on the main memory properties (latency and bandwidth), different cache organizations result in the lowest WCET. The evaluation reveals that for certain cache configurations, the analyzed hit rate is comparable to the average case hit rate obtained by measurements. We believe that an early architecture exploration by means of static timing analysis techniques helps to identify configurations suitable for hard real-time systems.