Computing Maximum Task Execution Times — A Graph-BasedApproach
Real-Time Systems
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
On Predicting Data Cache Behavior for Real-Time Systems
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
A Method to Improve the Estimated Worst-Case Performance of Data Caching
RTCSA '99 Proceedings of the Sixth International Conference on Real-Time Computing Systems and Applications
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
Data Caches in Multitasking Hard Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
An object-aware memory architecture
Science of Computer Programming - Special issue on five perspectives on modern memory management: Systems, hardware and theory
The case for the precision timed (PRET) machine
Proceedings of the 44th annual Design Automation Conference
jamuth: an IP processor core for embedded Java real-time systems
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
A Java processor architecture for embedded real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
Predictable programming on a precision timed architecture
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Time-predictable Cache Organization
STFSSD '09 Proceedings of the 2009 Software Technologies for Future Dependable Distributed Systems
Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
Data caching, garbage collection, and the Java memory model
Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems
Implementing time-predictable load and store operations
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Towards Time-Predictable Data Caches for Chip-Multiprocessors
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
Worst-case execution time analysis for a Java processor
Software—Practice & Experience
Precise and Efficient FIFO-Replacement Analysis Based on Static Phase Detection
ECRTS '10 Proceedings of the 2010 22nd Euromicro Conference on Real-Time Systems
Time-Predictable Out-of-Order Execution for Hard Real-Time Systems
IEEE Transactions on Computers
WCET driven design space exploration of an object cache
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
The embedded Java benchmark suite JemBench
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
A Time-Predictable Object Cache
ISORC '11 Proceedings of the 2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing
Hard real-time garbage collection for a Java chip multi-processor
Proceedings of the 9th International Workshop on Java Technologies for Real-Time and Embedded Systems
Concurrency and Computation: Practice & Experience
On the scalability of time-predictable chip-multiprocessing
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
Data cache organization for accurate timing analysis
Real-Time Systems
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Hard real-time systems need a time-predictable computing platform to enable static worst-case execution time (WCET) analysis. All performance-enhancing features need to be WCET analyzable. However, standard data caches containing heap-allocated data are very hard to analyze statically. In this paper we explore a new object cache design, which is driven by the capabilities of static WCET analysis. Simulations of standard benchmarks estimating the expected average case performance usually drive computer architecture design. The design decisions derived from this methodology do not necessarily result in a WCET analysis-friendly design. Aiming for a time-predictable design, we therefore propose to employ WCET analysis techniques for the design space exploration of processor architectures. We evaluated different object cache configurations using static analysis techniques. The number of field accesses that can be statically classified as hits is considerable. The analyzed number of cache miss cycles is 3–46% of the access cycles needed without a cache, which agrees with trends obtained using simulations. Standard data caches perform comparably well in the average case, but accesses to heap data result in overly pessimistic WCET estimations. We therefore believe that an early architecture exploration by means of static timing analysis techniques helps to identify configurations suitable for hard real-time systems. Copyright © 2011 John Wiley & Sons, Ltd.