Hardware compilation of sequential ada
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Ada-Europe '02 Proceedings of the 7th Ada-Europe International Conference on Reliable Software Technologies
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SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
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RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Data cache locking for tight timing calculations
ACM Transactions on Embedded Computing Systems (TECS)
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
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EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Towards Time-Predictable Data Caches for Chip-Multiprocessors
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
WCET analysis of instruction cache hierarchies
Journal of Systems Architecture: the EUROMICRO Journal
Cache-Aware development of high-integrity systems
Ada-Europe'10 Proceedings of the 15th Ada-Europe international conference on Reliable Software Technologies
Worst-case execution time analysis-driven object cache design
Concurrency and Computation: Practice & Experience
Static analysis of the worst-case memory performance for irregular codes with indirections
ACM Transactions on Architecture and Code Optimization (TACO)
Data cache organization for accurate timing analysis
Real-Time Systems
LP-NUCA: networks-in-cache for high-performance low-power embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Address independent estimation of the boundaries of cache performance
Microprocessors & Microsystems
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This paper presents a method for tight prediction of worst-case performance of data caches in high-performance real-time systems. Our approach is to distinguish between data structures that exhibit a predictable versus unpredictable cache behavior. Cache performance of accesses to predictable data structures can be automatically and accurately determined by our method whereas we let accesses to unpredictable data structures bypass the cache to simplify and improve the analysis. Through experimentation with a number of benchmark programs, we show that a vast majority of data accesses stems from predictable data structures. We analyze what kind of data structures that fall into this category.Remarkably, we find that all data structures in five out of the seven programs are predictable and will lead to a worst-case cache performance which is as high as the real performance. Moreover, for the remaining two benchmarks a majority of the accesses go to predictable data structures. Hence, empirically our data suggest that data caching is expected to improve worst-case performance considerably using our method.