Calculating the maximum, execution time of real-time programs
Real-Time Systems
Compiler support for software-based cache partitioning
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Static cache simulation and its applications
Static cache simulation and its applications
Computing Maximum Task Execution Times — A Graph-BasedApproach
Real-Time Systems
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
On Predicting Data Cache Behavior for Real-Time Systems
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
A Method to Improve the Estimated Worst-Case Performance of Data Caching
RTCSA '99 Proceedings of the Sixth International Conference on Real-Time Computing Systems and Applications
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
A Modular & Retargetable Framework for Tree-Based WCET Analysis
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
Accurate estimation of cache-related preemption delay
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Data Caches in Multitasking Hard Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
RTAS '05 Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium
Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
Modeling out-of-order processors for WCET analysis
Real-Time Systems
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
Performance evaluation of exclusive cache hierarchies
ISPASS '04 Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software
Timing predictability of cache replacement policies
Real-Time Systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Relative competitive analysis of cache replacement policies
Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
Improving the First-Miss Computation in Set-Associative Instruction Caches
ECRTS '08 Proceedings of the 2008 Euromicro Conference on Real-Time Systems
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Unified Cache Modeling for WCET Analysis and Layout Optimizations
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
A Unified WCET analysis framework for multicore platforms
ACM Transactions on Embedded Computing Systems (TECS)
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With the advent of increasingly complex hardware in real-time embedded systems (processors with performance enhancing features such as pipelines, caches, multiple cores), most embedded processors use a hierarchy of caches. While much research has been devoted to the prediction of Worst-Case Execution Times (WCETs) in the presence of a single level of cache (instruction caches, data caches, impact of cache replacement policies), very little research has focused on WCET estimations in the presence of cache hierarchies. In this paper, we propose a safe static instruction cache analysis method for multi-level caches. Variations of the method are presented to model different cache hierarchy management policies between cache levels: non-inclusive, inclusive and exclusive cache hierarchies. The method supports multiple replacement policies. The proposed method is experimented on medium-size benchmarks and a larger application. We show that the method is tight in the case of non-inclusive caches hierarchies and exclusive caches hierarchies, provided that all cache levels use the Least Recently Used (LRU) replacement policy. We further evaluate the additional pessimism when inclusion is enforced or when a non-LRU replacement policy is used.